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| author | Tom Rini <trini@konsulko.com> | 2021-07-24 23:41:25 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2021-07-24 23:41:25 +0300 |
| commit | ec22c365e3d21c8a5c20413d537042527b33a6cf (patch) | |
| tree | 06a613b648aafcc6b35e195cab65f366b6f38e7f /doc/board | |
| parent | 7d4ce5ea53bdf4be8a951154c65ceef4b389fea7 (diff) | |
| parent | d75f48a83dc4998a49a4c35e80a9eab91566df30 (diff) | |
| download | u-boot-ec22c365e3d21c8a5c20413d537042527b33a6cf.tar.xz | |
Merge tag 'efi-2021-10-rc1-3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-10-rc1-3
Documentation:
provide Makefile documentation
SMBIOS:
generate BIOS release date based on UEFI version
improve error handling in SMBIOS table generation
UEFI:
correct handling of signed capsule if authentication if off
Diffstat (limited to 'doc/board')
| -rw-r--r-- | doc/board/emulation/index.rst | 1 | ||||
| -rw-r--r-- | doc/board/openpiton/riscv64.rst | 19 |
2 files changed, 9 insertions, 11 deletions
diff --git a/doc/board/emulation/index.rst b/doc/board/emulation/index.rst index be66b6bb67..b5b6c3fa0d 100644 --- a/doc/board/emulation/index.rst +++ b/doc/board/emulation/index.rst @@ -11,4 +11,3 @@ Emulation qemu-ppce500 qemu-riscv qemu-x86 - qemu_capsule_update diff --git a/doc/board/openpiton/riscv64.rst b/doc/board/openpiton/riscv64.rst index 253b37c41c..3a97793f07 100644 --- a/doc/board/openpiton/riscv64.rst +++ b/doc/board/openpiton/riscv64.rst @@ -3,8 +3,6 @@ Openpiton RISC-V SoC ==================== -OpenPiton RISC-V SoC --------------------- OpenPiton is an open source, manycore processor and research platform. It is a tiled manycore framework scalable from one to 1/2 billion cores. It supports a number of ISAs including RISC-V with its P-Mesh cache coherence protocol and @@ -14,21 +12,23 @@ running full-stack Debian linux. RISC-V Standard Bootflow ------------------------- + Currently, OpenPiton implements RISC-V standard bootflow in the following steps mover.S -> u-boot-spl -> opensbi -> u-boot -> Linux This board supports S-mode u-boot as well as M-mode SPL Building OpenPition --------------------- + If you'd like to build OpenPiton, please go to OpenPiton github repo (at https://github.com/PrincetonUniversity/openpiton) to build from the latest changes Building Images ---------------------------- +--------------- SPL ---- +~~~ 1. Add the RISC-V toolchain to your PATH. 2. Setup ARCH & cross compilation environment variable: @@ -42,7 +42,7 @@ SPL 4. make U-Boot ------- +~~~~~~ 1. Add the RISC-V toolchain to your PATH. 2. Setup ARCH & cross compilation environment variable: @@ -55,9 +55,8 @@ U-Boot 3. make openpiton_riscv64_defconfig 4. make - opensbi -------- +~~~~~~~ 1. Add the RISC-V toolchain to your PATH. 2. Setup ARCH & cross compilation environment variable: @@ -70,9 +69,9 @@ opensbi 3. Go to OpenSBI directory 4. make PLATFORM=fpga/openpiton FW_PAYLOAD_PATH=<path to u-boot-nodtb.bin> +Using fw_payload.bin with Linux +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Using fw_payload.bin with linux -------------------------------- Put the generated fw_payload.bin into the /boot directory on the root filesystem, plug in the SD card, then flash the bitstream. Linux will boot automatically. @@ -81,7 +80,7 @@ Booting Once you plugin the sdcard and power up, you should see the U-Boot prompt. Sample Dual-core Debian boot log from OpenPiton ------------------------------------------------ +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ .. code-block:: none |