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author | Breno Lima <breno.lima@nxp.com> | 2018-07-21 03:48:10 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2018-07-24 16:25:23 +0300 |
commit | ad7061ed742e1312289644268859a0f4b512aaee (patch) | |
tree | ff7d8bfd460f81d0ccf3d0a83661106e72c473d1 /doc/device-tree-bindings/phy | |
parent | 4a8b6e0101f8a5dd2c4629a872d4287c70dbe5e2 (diff) | |
download | u-boot-ad7061ed742e1312289644268859a0f4b512aaee.tar.xz |
doc: Move device tree bindings documentation to doc/device-tree-bindings
Currently the U-Boot project contains 2 documentation directories:
- doc/
- Documentation/
The Documentation directory only contains device tree bindings related
content, so move the 3 files to doc/device-tree-bindings/.
Signed-off-by: Breno Lima <breno.lima@nxp.com>
Diffstat (limited to 'doc/device-tree-bindings/phy')
-rw-r--r-- | doc/device-tree-bindings/phy/no-op.txt | 16 | ||||
-rw-r--r-- | doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt | 73 |
2 files changed, 89 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/phy/no-op.txt b/doc/device-tree-bindings/phy/no-op.txt new file mode 100644 index 0000000000..a3381122e6 --- /dev/null +++ b/doc/device-tree-bindings/phy/no-op.txt @@ -0,0 +1,16 @@ +NOP PHY driver + +This driver is used to stub PHY operations in a driver (USB, SATA). +This is useful when the 'client' driver (USB, SATA, ...) uses the PHY framework +and there is no actual PHY harwdare to drive. + +Required properties: +- compatible : must contain "nop-phy" +- #phy-cells : must contain <0> + +Example: + +nop_phy { + compatible = "nop-phy"; + #phy-cells = <0>; +}; diff --git a/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt new file mode 100644 index 0000000000..725ae71ae6 --- /dev/null +++ b/doc/device-tree-bindings/phy/phy-stm32-usbphyc.txt @@ -0,0 +1,73 @@ +STMicroelectronics STM32 USB HS PHY controller + +The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI +switch. It controls PHY configuration and status, and the UTMI+ switch that +selects either OTG or HOST controller for the second PHY port. It also sets +PLL configuration. + +USBPHYC + |_ PLL + | + |_ PHY port#1 _________________ HOST controller + | _ | + | / 1|________________| + |_ PHY port#2 ----| |________________ + | \_0| | + |_ UTMI switch_______| OTG controller + + +Phy provider node +================= + +Required properties: +- compatible: must be "st,stm32mp1-usbphyc" +- reg: address and length of the usb phy control register set +- clocks: phandle + clock specifier for the PLL phy clock +- #address-cells: number of address cells for phys sub-nodes, must be <1> +- #size-cells: number of size cells for phys sub-nodes, must be <0> + +Optional properties: +- assigned-clocks: phandle + clock specifier for the PLL phy clock +- assigned-clock-parents: the PLL phy clock parent +- resets: phandle + reset specifier + +Required nodes: one sub-node per port the controller provides. + +Phy sub-nodes +============== + +Required properties: +- reg: phy port index +- phy-supply: phandle to the regulator providing 3V3 power to the PHY, + see phy-bindings.txt in the same directory. +- vdda1v1-supply: phandle to the regulator providing 1V1 power to the PHY +- vdda1v8-supply: phandle to the regulator providing 1V8 power to the PHY +- #phy-cells: see phy-bindings.txt in the same directory, must be <0> for PHY + port#1 and must be <1> for PHY port#2, to select USB controller + + +Example: + usbphyc: usb-phy@5a006000 { + compatible = "st,stm32mp1-usbphyc"; + reg = <0x5a006000 0x1000>; + clocks = <&rcc_clk USBPHY_K>; + resets = <&rcc_rst USBPHY_R>; + #address-cells = <1>; + #size-cells = <0>; + + usbphyc_port0: usb-phy@0 { + reg = <0>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18> + #phy-cells = <0>; + }; + + usbphyc_port1: usb-phy@1 { + reg = <1>; + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18> + #phy-cells = <1>; + }; + }; |