doc: binding: rename directory ram to memory-controller

Alignment with kernel directory name as it have already bindings for
DDR controllers in the directory:
Documentation/devicetree/bindings/memory-controller

PS: the drivers using RAM u-class should be associated with
    this binding directory

Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>

3 files changed, 0 insertions, 403 deletions

diff --git a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt b/doc/device-tree-bindings/ram/k3-am654-ddrss.txt
deleted file mode 100644
index 4ed731c524..0000000000
--- a/doc/device-tree-bindings/ram/k3-am654-ddrss.txt
+++ /dev/null
@@ -1,46 +0,0 @@
-Texas Instruments' K3 AM654 DDRSS
-=================================
-
-K3 based AM654 devices has DDR memory subsystem that comprises
-Synopys DDR controller, Synopsis DDR phy and wrapper logic to
-integrate these blocks into the device. This DDR subsystem
-provides an interface to external SDRAM devices. This DDRSS driver
-adds support for the initialization of the external SDRAM devices by
-configuring the DDRSS registers and using the buitin PHY
-initialization routines.
-
-DDRSS device node:
-==================
-Required properties:
---------------------
-- compatible:		Shall be: "ti,am654-ddrss"
-- reg-names 		ss - Map the sub system wrapper logic region
-			ctl - Map the controller region
-			phy - Map the PHY region
-- reg:			Contains the register map per reg-names.
-- power-domains:	Should contain a phandle to a PM domain provider node
-			and an args specifier containing the DDRSS device id
-			value. This property is as per the binding,
-			doc/device-tree-bindings/power/ti,sci-pm-domain.txt
-- clocks:		Must contain an entry for enabling DDR clock. Should
-			be defined as per the appropriate clock bindings consumer
-			usage in doc/device-tree-bindings/clock/ti,sci-clk.txt
-
-
-Optional Properties:
---------------------
-- clock-frequency:	Frequency at which DDR pll should be locked.
-			If not provided, default frequency will be used.
-
-Example (AM65x):
-================
-		memory-controller: memory-controller@298e000 {
-			compatible = "ti,am654-ddrss";
-			reg = <0x0298e000 0x200>,
-				<0x02980000 0x4000>,
-				<0x02988000 0x2000>;
-			reg-names = "ss", "ctl", "phy";
-			clocks = <&k3_clks 20 0>;
-			power-domains = <&k3_pds 20>;
-			u-boot,dm-spl;
-		};
diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt
deleted file mode 100644
index 99f76d515f..0000000000
--- a/doc/device-tree-bindings/ram/st,stm32-fmc.txt
+++ /dev/null
@@ -1,58 +0,0 @@
-ST, stm32 flexible memory controller Drive
-Required properties:
-- compatible	: "st,stm32-fmc"
-- reg		: fmc controller base address
-- clocks	: fmc controller clock
-u-boot,dm-pre-reloc: flag to initialize memory before relocation.
-
-on-board sdram memory attributes:
-- st,sdram-control : parameters for sdram configuration, in this order:
-  number of columns
-  number of rows
-  memory width
-  number of intenal banks in memory
-  cas latency
-  read burst enable or disable
-  read pipe delay
-
-- st,sdram-timing: timings for sdram, in this order:
-  tmrd
-  txsr
-  tras
-  trc
-  trp
-  trcd
-
-There is device tree include file at :
-include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing
-parameters as MACROS.
-
-Example:
-	fmc: fmc@A0000000 {
-	     compatible = "st,stm32-fmc";
-	     reg = <0xA0000000 0x1000>;
-	     clocks = <&rcc 0 64>;
-	     u-boot,dm-pre-reloc;
-	};
-
-	&fmc {
-		pinctrl-0 = <&fmc_pins>;
-		pinctrl-names = "default";
-		status = "okay";
-
-		/* sdram memory configuration from sdram datasheet */
-		bank1: bank@0 {
-		       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
-						CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
-		       st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
-						TRCD_18>;
-		};
-
-		/* sdram memory configuration from sdram datasheet */
-		bank2: bank@1 {
-		       st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2
-						CAS_3 RD_BURST_EN RD_PIPE_DL_0>;
-		       st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18
-						TRCD_18>;
-		};
-	}
diff --git a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt b/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
deleted file mode 100644
index 3028636c45..0000000000
--- a/doc/device-tree-bindings/ram/st,stm32mp1-ddr.txt
+++ /dev/null
@@ -1,299 +0,0 @@
-ST,stm32mp1 DDR3/LPDDR2/LPDDR3 Controller (DDRCTRL and DDRPHYC)
-
---------------------
-Required properties:
---------------------
-- compatible	: Should be "st,stm32mp1-ddr"
-- reg		: controleur (DDRCTRL) and phy (DDRPHYC) base address
-- clocks	: controller clocks handle
-- clock-names	: associated controller clock names
-		  the "ddrphyc" clock is used to check the DDR frequency
-		  at phy level according the expected value in "mem-speed" field
-
-the next attributes are DDR parameters, they are generated by DDR tools
-included in STM32 Cube tool
-
-info attributes:
-----------------
-- st,mem-name	: name for DDR configuration, simple string for information
-- st,mem-speed	: DDR expected speed for the setting in MHz
-- st,mem-size	: DDR mem size in byte
-
-
-controlleur attributes:
------------------------
-- st,ctl-reg	: controleur values depending of the DDR type
-		  (DDR3/LPDDR2/LPDDR3)
-	for STM32MP15x: 25 values are requested in this order
-		MSTR
-		MRCTRL0
-		MRCTRL1
-		DERATEEN
-		DERATEINT
-		PWRCTL
-		PWRTMG
-		HWLPCTL
-		RFSHCTL0
-		RFSHCTL3
-		CRCPARCTL0
-		ZQCTL0
-		DFITMG0
-		DFITMG1
-		DFILPCFG0
-		DFIUPD0
-		DFIUPD1
-		DFIUPD2
-		DFIPHYMSTR
-		ODTMAP
-		DBG0
-		DBG1
-		DBGCMD
-		POISONCFG
-		PCCFG
-
-- st,ctl-timing	: controleur values depending of frequency and timing parameter
-		  of DDR
-	for STM32MP15x: 12 values are requested in this order
-		RFSHTMG
-		DRAMTMG0
-		DRAMTMG1
-		DRAMTMG2
-		DRAMTMG3
-		DRAMTMG4
-		DRAMTMG5
-		DRAMTMG6
-		DRAMTMG7
-		DRAMTMG8
-		DRAMTMG14
-		ODTCFG
-
-- st,ctl-map	: controleur values depending of address mapping
-	for STM32MP15x: 9 values are requested in this order
-		ADDRMAP1
-		ADDRMAP2
-		ADDRMAP3
-		ADDRMAP4
-		ADDRMAP5
-		ADDRMAP6
-		ADDRMAP9
-		ADDRMAP10
-		ADDRMAP11
-
-- st,ctl-perf	: controleur values depending of performance and scheduling
-	for STM32MP15x: 17 values are requested in this order
-		SCHED
-		SCHED1
-		PERFHPR1
-		PERFLPR1
-		PERFWR1
-		PCFGR_0
-		PCFGW_0
-		PCFGQOS0_0
-		PCFGQOS1_0
-		PCFGWQOS0_0
-		PCFGWQOS1_0
-		PCFGR_1
-		PCFGW_1
-		PCFGQOS0_1
-		PCFGQOS1_1
-		PCFGWQOS0_1
-		PCFGWQOS1_1
-
-phyc attributes:
-----------------
-- st,phy-reg	: phy values depending of the DDR type (DDR3/LPDDR2/LPDDR3)
-	for STM32MP15x: 10 values are requested in this order
-		PGCR
-		ACIOCR
-		DXCCR
-		DSGCR
-		DCR
-		ODTCR
-		ZQ0CR1
-		DX0GCR
-		DX1GCR
-		DX2GCR
-		DX3GCR
-
-- st,phy-timing	: phy values depending of frequency and timing parameter of DDR
-	for STM32MP15x: 10 values are requested in this order
-		PTR0
-		PTR1
-		PTR2
-		DTPR0
-		DTPR1
-		DTPR2
-		MR0
-		MR1
-		MR2
-		MR3
-
-- st,phy-cal	: phy cal depending of calibration or tuning of DDR
-	for STM32MP15x: 12 values are requested in this order
-		DX0DLLCR
-		DX0DQTR
-		DX0DQSTR
-		DX1DLLCR
-		DX1DQTR
-		DX1DQSTR
-		DX2DLLCR
-		DX2DQTR
-		DX2DQSTR
-		DX3DLLCR
-		DX3DQTR
-		DX3DQSTR
-
-Example:
-
-/ {
-	soc {
-		u-boot,dm-spl;
-
-		ddr: ddr@0x5A003000{
-			u-boot,dm-spl;
-			u-boot,dm-pre-reloc;
-
-			compatible = "st,stm32mp1-ddr";
-
-			reg = <0x5A003000 0x550
-			       0x5A004000 0x234>;
-
-			clocks = <&rcc_clk AXIDCG>,
-				 <&rcc_clk DDRC1>,
-				 <&rcc_clk DDRC2>,
-				 <&rcc_clk DDRPHYC>,
-				 <&rcc_clk DDRCAPB>,
-				 <&rcc_clk DDRPHYCAPB>;
-
-			clock-names = "axidcg",
-				      "ddrc1",
-				      "ddrc2",
-				      "ddrphyc",
-				      "ddrcapb",
-				      "ddrphycapb";
-
-			st,mem-name = "DDR3 2x4Gb 533MHz";
-			st,mem-speed = <533>;
-			st,mem-size = <0x40000000>;
-
-			st,ctl-reg = <
-				0x00040401 /*MSTR*/
-				0x00000010 /*MRCTRL0*/
-				0x00000000 /*MRCTRL1*/
-				0x00000000 /*DERATEEN*/
-				0x00800000 /*DERATEINT*/
-				0x00000000 /*PWRCTL*/
-				0x00400010 /*PWRTMG*/
-				0x00000000 /*HWLPCTL*/
-				0x00210000 /*RFSHCTL0*/
-				0x00000000 /*RFSHCTL3*/
-				0x00000000 /*CRCPARCTL0*/
-				0xC2000040 /*ZQCTL0*/
-				0x02050105 /*DFITMG0*/
-				0x00000202 /*DFITMG1*/
-				0x07000000 /*DFILPCFG0*/
-				0xC0400003 /*DFIUPD0*/
-				0x00000000 /*DFIUPD1*/
-				0x00000000 /*DFIUPD2*/
-				0x00000000 /*DFIPHYMSTR*/
-				0x00000001 /*ODTMAP*/
-				0x00000000 /*DBG0*/
-				0x00000000 /*DBG1*/
-				0x00000000 /*DBGCMD*/
-				0x00000000 /*POISONCFG*/
-				0x00000010 /*PCCFG*/
-			>;
-
-			st,ctl-timing = <
-				0x0080008A /*RFSHTMG*/
-				0x121B2414 /*DRAMTMG0*/
-				0x000D041B /*DRAMTMG1*/
-				0x0607080E /*DRAMTMG2*/
-				0x0050400C /*DRAMTMG3*/
-				0x07040407 /*DRAMTMG4*/
-				0x06060303 /*DRAMTMG5*/
-				0x02020002 /*DRAMTMG6*/
-				0x00000202 /*DRAMTMG7*/
-				0x00001005 /*DRAMTMG8*/
-				0x000D041B /*DRAMTMG1*/4
-				0x06000600 /*ODTCFG*/
-			>;
-
-			st,ctl-map = <
-				0x00080808 /*ADDRMAP1*/
-				0x00000000 /*ADDRMAP2*/
-				0x00000000 /*ADDRMAP3*/
-				0x00001F1F /*ADDRMAP4*/
-				0x07070707 /*ADDRMAP5*/
-				0x0F070707 /*ADDRMAP6*/
-				0x00000000 /*ADDRMAP9*/
-				0x00000000 /*ADDRMAP10*/
-				0x00000000 /*ADDRMAP11*/
-			>;
-
-			st,ctl-perf = <
-				0x00001201 /*SCHED*/
-				0x00001201 /*SCHED*/1
-				0x01000001 /*PERFHPR1*/
-				0x08000200 /*PERFLPR1*/
-				0x08000400 /*PERFWR1*/
-				0x00010000 /*PCFGR_0*/
-				0x00000000 /*PCFGW_0*/
-				0x02100B03 /*PCFGQOS0_0*/
-				0x00800100 /*PCFGQOS1_0*/
-				0x01100B03 /*PCFGWQOS0_0*/
-				0x01000200 /*PCFGWQOS1_0*/
-				0x00010000 /*PCFGR_1*/
-				0x00000000 /*PCFGW_1*/
-				0x02100B03 /*PCFGQOS0_1*/
-				0x00800000 /*PCFGQOS1_1*/
-				0x01100B03 /*PCFGWQOS0_1*/
-				0x01000200 /*PCFGWQOS1_1*/
-			>;
-
-			st,phy-reg = <
-				0x01442E02 /*PGCR*/
-				0x10400812 /*ACIOCR*/
-				0x00000C40 /*DXCCR*/
-				0xF200001F /*DSGCR*/
-				0x0000000B /*DCR*/
-				0x00010000 /*ODTCR*/
-				0x0000007B /*ZQ0CR1*/
-				0x0000CE81 /*DX0GCR*/
-				0x0000CE81 /*DX1GCR*/
-				0x0000CE81 /*DX2GCR*/
-				0x0000CE81 /*DX3GCR*/
-			>;
-
-			st,phy-timing = <
-				0x0022A41B /*PTR0*/
-				0x047C0740 /*PTR1*/
-				0x042D9C80 /*PTR2*/
-				0x369477D0 /*DTPR0*/
-				0x098A00D8 /*DTPR1*/
-				0x10023600 /*DTPR2*/
-				0x00000830 /*MR0*/
-				0x00000000 /*MR1*/
-				0x00000208 /*MR2*/
-				0x00000000 /*MR3*/
-			>;
-
-			st,phy-cal = <
-				0x40000000 /*DX0DLLCR*/
-				0xFFFFFFFF /*DX0DQTR*/
-				0x3DB02000 /*DX0DQSTR*/
-				0x40000000 /*DX1DLLCR*/
-				0xFFFFFFFF /*DX1DQTR*/
-				0x3DB02000 /*DX1DQSTR*/
-				0x40000000 /*DX2DLLCR*/
-				0xFFFFFFFF /*DX2DQTR*/
-				0x3DB02000 /*DX2DQSTR*/
-				0x40000000 /*DX3DLLCR*/
-				0xFFFFFFFF /*DX3DQTR*/
-				0x3DB02000 /*DX3DQSTR*/
-			>;
-
-			status = "okay";
-		};
-	};
-};