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author | Vikas Manocha <vikas.manocha@st.com> | 2017-04-11 01:02:53 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2017-05-08 18:39:03 +0300 |
commit | fd198ee1a8c5de79d31df9ca3c04d6d783868690 (patch) | |
tree | 48139f8b924dcb1a09a20ad0c20708c1c6651059 /doc/device-tree-bindings/ram | |
parent | 910a52ede3d7cf75b3157b9a3ef6f40879a38194 (diff) | |
download | u-boot-fd198ee1a8c5de79d31df9ca3c04d6d783868690.tar.xz |
ARM: DT: stm32f7: add sdram pin contol node
Also added DT binding doc for stm32 fmc(flexible memory controller).
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
cc: Christophe KERELLO <christophe.kerello@st.com>
Diffstat (limited to 'doc/device-tree-bindings/ram')
-rw-r--r-- | doc/device-tree-bindings/ram/st,stm32-fmc.txt | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/ram/st,stm32-fmc.txt b/doc/device-tree-bindings/ram/st,stm32-fmc.txt new file mode 100644 index 0000000000..3d1392c764 --- /dev/null +++ b/doc/device-tree-bindings/ram/st,stm32-fmc.txt @@ -0,0 +1,51 @@ +ST, stm32 flexible memory controller Drive +Required properties: +- compatible : "st,stm32-fmc" +- reg : fmc controller base address +- clocks : fmc controller clock +u-boot,dm-pre-reloc: flag to initialize memory before relocation. + +on-board sdram memory attributes: +- st,sdram-control : parameters for sdram configuration, in this order: + number of columns + number of rows + memory width + number of intenal banks in memory + cas latency + read burst enable or disable + read pipe delay + +- st,sdram-timing: timings for sdram, in this order: + tmrd + txsr + tras + trc + trp + trcd + +There is device tree include file at : +include/dt-bindings/memory/stm32-sdram.h to define sdram control and timing +parameters as MACROS. + +Example: + fmc: fmc@A0000000 { + compatible = "st,stm32-fmc"; + reg = <0xA0000000 0x1000>; + clocks = <&rcc 0 64>; + u-boot,dm-pre-reloc; + }; + + &fmc { + pinctrl-0 = <&fmc_pins>; + pinctrl-names = "default"; + status = "okay"; + + mr-nbanks = <1>; + /* sdram memory configuration from sdram datasheet */ + bank1: bank@0 { + st,sdram-control = /bits/ 8 <NO_COL_8 NO_ROW_12 MWIDTH_16 BANKS_2 + CAS_3 RD_BURST_EN RD_PIPE_DL_0>; + st,sdram-timing = /bits/ 8 <TMRD_1 TXSR_60 TRAS_42 TRC_60 TRP_18 + TRCD_18>; + }; +} |