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author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2021-08-02 19:08:36 +0300 |
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committer | Heinrich Schuchardt <xypron.glpk@gmx.de> | 2021-08-14 21:54:41 +0300 |
commit | 551a959a8c11e7f3452e0c2f24db85dffebc1e91 (patch) | |
tree | e0fac2bab44a347e60596e176f22002517ddbb18 /doc/device-tree-bindings/spi | |
parent | 6a055c0f91418b78949b901147a63f2a4e26c9ab (diff) | |
download | u-boot-551a959a8c11e7f3452e0c2f24db85dffebc1e91.tar.xz |
doc: stm32mp1: add page for device tree bindings
With device tree binding migration to yaml it is difficult to synchronize
the binding from Linux kernel to U-Boot.
Instead of maintaining the same dt bindings, this patch adds in the U-Boot
documentation the path to the device tree bindings in Linux kernel for
STMicroelectronics devices, when they are used without modification.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com>
Add links for referenced text files.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Diffstat (limited to 'doc/device-tree-bindings/spi')
-rw-r--r-- | doc/device-tree-bindings/spi/spi-stm32-qspi.txt | 44 |
1 files changed, 0 insertions, 44 deletions
diff --git a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt b/doc/device-tree-bindings/spi/spi-stm32-qspi.txt deleted file mode 100644 index adeeb63e84..0000000000 --- a/doc/device-tree-bindings/spi/spi-stm32-qspi.txt +++ /dev/null @@ -1,44 +0,0 @@ -* STMicroelectronics Quad Serial Peripheral Interface(QSPI) - -Required properties: -- compatible: should be "st,stm32f469-qspi" -- reg: the first contains the register location and length. - the second contains the memory mapping address and length -- reg-names: should contain the reg names "qspi" "qspi_mm" -- interrupts: should contain the interrupt for the device -- clocks: the phandle of the clock needed by the QSPI controller -- A pinctrl must be defined to set pins in mode of operation for QSPI transfer - -Optional properties: -- resets: must contain the phandle to the reset controller. - -A spi flash (NOR/NAND) must be a child of spi node and could have some -properties. Also see jedec,spi-nor.txt. - -Required properties: -- reg: chip-Select number (QSPI controller may connect 2 flashes) -- spi-max-frequency: max frequency of spi bus - -Optional property: -- spi-rx-bus-width: see ./spi-bus.txt for the description - -Example: - -qspi: spi@a0001000 { - compatible = "st,stm32f469-qspi"; - reg = <0xa0001000 0x1000>, <0x90000000 0x10000000>; - reg-names = "qspi", "qspi_mm"; - interrupts = <91>; - resets = <&rcc STM32F4_AHB3_RESET(QSPI)>; - clocks = <&rcc 0 STM32F4_AHB3_CLOCK(QSPI)>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_qspi0>; - - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-rx-bus-width = <4>; - spi-max-frequency = <108000000>; - ... - }; -}; |