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authorBreno Matheus Lima <breno.lima@nxp.com>2019-06-05 21:18:30 +0300
committerTom Rini <trini@konsulko.com>2019-06-20 17:57:08 +0300
commit656d8da9d2862afd293ae678d37a486d34b76ca2 (patch)
tree405420ece9ddde3c6e8f66ab65867d128d7761be /doc/device-tree-bindings
parent894e235f145b4f397a474f22c7c604ae925eb114 (diff)
downloadu-boot-656d8da9d2862afd293ae678d37a486d34b76ca2.tar.xz
doc: Remove duplicated documentation directory
Commit ad7061ed742e ("doc: Move device tree bindings documentation to doc/device-tree-bindings") moved all device tree binding documentation to doc/device-tree-bindings directory. The current U-Boot project still have two documentation directories: - doc/ - Documentation/ Move all documentation and sphinx files to doc directory so all content can be in a common place. Signed-off-by: Breno Lima <breno.lima@nxp.com>
Diffstat (limited to 'doc/device-tree-bindings')
-rw-r--r--doc/device-tree-bindings/arm/l2c2x0.txt114
-rw-r--r--doc/device-tree-bindings/axi/gdsys,ihs_axi.txt22
-rw-r--r--doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt46
-rw-r--r--doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt23
-rw-r--r--doc/device-tree-bindings/cpu/fsl,mpc83xx.txt34
-rw-r--r--doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt24
-rw-r--r--doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt20
-rw-r--r--doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt19
-rw-r--r--doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt19
-rw-r--r--doc/device-tree-bindings/misc/misc/gdsys,soc.txt16
-rw-r--r--doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt314
-rw-r--r--doc/device-tree-bindings/reserved-memory/reserved-memory.txt136
-rw-r--r--doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt21
13 files changed, 808 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/arm/l2c2x0.txt b/doc/device-tree-bindings/arm/l2c2x0.txt
new file mode 100644
index 0000000000..fbe6cb21f4
--- /dev/null
+++ b/doc/device-tree-bindings/arm/l2c2x0.txt
@@ -0,0 +1,114 @@
+* ARM L2 Cache Controller
+
+ARM cores often have a separate L2C210/L2C220/L2C310 (also known as PL210/PL220/
+PL310 and variants) based level 2 cache controller. All these various implementations
+of the L2 cache controller have compatible programming models (Note 1).
+Some of the properties that are just prefixed "cache-*" are taken from section
+3.7.3 of the Devicetree Specification which can be found at:
+https://www.devicetree.org/specifications/
+
+The ARM L2 cache representation in the device tree should be done as follows:
+
+Required properties:
+
+- compatible : should be one of:
+ "arm,pl310-cache"
+ "arm,l220-cache"
+ "arm,l210-cache"
+ "bcm,bcm11351-a2-pl310-cache": DEPRECATED by "brcm,bcm11351-a2-pl310-cache"
+ "brcm,bcm11351-a2-pl310-cache": For Broadcom bcm11351 chipset where an
+ offset needs to be added to the address before passing down to the L2
+ cache controller
+ "marvell,aurora-system-cache": Marvell Controller designed to be
+ compatible with the ARM one, with system cache mode (meaning
+ maintenance operations on L1 are broadcasted to the L2 and L2
+ performs the same operation).
+ "marvell,aurora-outer-cache": Marvell Controller designed to be
+ compatible with the ARM one with outer cache mode.
+ "marvell,tauros3-cache": Marvell Tauros3 cache controller, compatible
+ with arm,pl310-cache controller.
+- cache-unified : Specifies the cache is a unified cache.
+- cache-level : Should be set to 2 for a level 2 cache.
+- reg : Physical base address and size of cache controller's memory mapped
+ registers.
+
+Optional properties:
+
+- arm,data-latency : Cycles of latency for Data RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Minimum valid values are 1. Controllers
+ without setup latency control should use a value of 0.
+- arm,tag-latency : Cycles of latency for Tag RAM accesses. Specifies 3 cells of
+ read, write and setup latencies. Controllers without setup latency control
+ should use 0. Controllers without separate read and write Tag RAM latency
+ values should only use the first cell.
+- arm,dirty-latency : Cycles of latency for Dirty RAMs. This is a single cell.
+- arm,filter-ranges : <start length> Starting address and length of window to
+ filter. Addresses in the filter window are directed to the M1 port. Other
+ addresses will go to the M0 port.
+- arm,io-coherent : indicates that the system is operating in an hardware
+ I/O coherent mode. Valid only when the arm,pl310-cache compatible
+ string is used.
+- interrupts : 1 combined interrupt.
+- cache-size : specifies the size in bytes of the cache
+- cache-sets : specifies the number of associativity sets of the cache
+- cache-block-size : specifies the size in bytes of a cache block
+- cache-line-size : specifies the size in bytes of a line in the cache,
+ if this is not specified, the line size is assumed to be equal to the
+ cache block size
+- cache-id-part: cache id part number to be used if it is not present
+ on hardware
+- wt-override: If present then L2 is forced to Write through mode
+- arm,double-linefill : Override double linefill enable setting. Enable if
+ non-zero, disable if zero.
+- arm,double-linefill-incr : Override double linefill on INCR read. Enable
+ if non-zero, disable if zero.
+- arm,double-linefill-wrap : Override double linefill on WRAP read. Enable
+ if non-zero, disable if zero.
+- arm,prefetch-drop : Override prefetch drop enable setting. Enable if non-zero,
+ disable if zero.
+- arm,prefetch-offset : Override prefetch offset value. Valid values are
+ 0-7, 15, 23, and 31.
+- arm,shared-override : The default behavior of the L220 or PL310 cache
+ controllers with respect to the shareable attribute is to transform "normal
+ memory non-cacheable transactions" into "cacheable no allocate" (for reads)
+ or "write through no write allocate" (for writes).
+ On systems where this may cause DMA buffer corruption, this property must be
+ specified to indicate that such transforms are precluded.
+- arm,parity-enable : enable parity checking on the L2 cache (L220 or PL310).
+- arm,parity-disable : disable parity checking on the L2 cache (L220 or PL310).
+- arm,outer-sync-disable : disable the outer sync operation on the L2 cache.
+ Some core tiles, especially ARM PB11MPCore have a faulty L220 cache that
+ will randomly hang unless outer sync operations are disabled.
+- prefetch-data : Data prefetch. Value: <0> (forcibly disable), <1>
+ (forcibly enable), property absent (retain settings set by firmware)
+- prefetch-instr : Instruction prefetch. Value: <0> (forcibly disable),
+ <1> (forcibly enable), property absent (retain settings set by
+ firmware)
+- arm,dynamic-clock-gating : L2 dynamic clock gating. Value: <0> (forcibly
+ disable), <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+- arm,standby-mode: L2 standby mode enable. Value <0> (forcibly disable),
+ <1> (forcibly enable), property absent (OS specific behavior,
+ preferably retain firmware settings)
+- arm,early-bresp-disable : Disable the CA9 optimization Early BRESP (PL310)
+- arm,full-line-zero-disable : Disable the CA9 optimization Full line of zero
+ write (PL310)
+
+Example:
+
+L2: cache-controller {
+ compatible = "arm,pl310-cache";
+ reg = <0xfff12000 0x1000>;
+ arm,data-latency = <1 1 1>;
+ arm,tag-latency = <2 2 2>;
+ arm,filter-ranges = <0x80000000 0x8000000>;
+ cache-unified;
+ cache-level = <2>;
+ interrupts = <45>;
+};
+
+Note 1: The description in this document doesn't apply to integrated L2
+ cache controllers as found in e.g. Cortex-A15/A7/A57/A53. These
+ integrated L2 controllers are assumed to be all preconfigured by
+ early secure boot code. Thus no need to deal with their configuration
+ in the kernel at all.
diff --git a/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt b/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt
new file mode 100644
index 0000000000..110788fa91
--- /dev/null
+++ b/doc/device-tree-bindings/axi/gdsys,ihs_axi.txt
@@ -0,0 +1,22 @@
+gdsys AXI busses of IHS FPGA devices
+
+Certain gdsys IHS FPGAs offer a interface to their built-in AXI bus with which
+the connected devices (usually IP cores) can be controlled via software.
+
+Required properties:
+- compatible: must be "gdsys,ihs_axi"
+- reg: describes the address and length of the AXI bus's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_axi_video0 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ compatible = "gdsys,ihs_axi";
+ reg = <0x170 0x10>;
+
+ axi_dev_1 {
+ ...
+ };
+};
diff --git a/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt b/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt
new file mode 100644
index 0000000000..28c1080d90
--- /dev/null
+++ b/doc/device-tree-bindings/board/gdsys,board_gazerbeam.txt
@@ -0,0 +1,46 @@
+gdsys Gazerbeam board driver
+
+This driver provides capabilities to access the gdsys Gazerbeam board's device
+information. Furthermore, phandles to some internal devices are provided for
+the board files.
+
+Required properties:
+- compatible: should be "gdsys,board_gazerbeam"
+- csb: phandle to the board's coherent system bus (CSB) device node
+- rxaui[0-3]: phandles to the rxaui control device nodes
+- fpga[0-1]: phandles to the board's gdsys FPGA device nodes
+- ioep[0-1]: phandles to the board's IO endpoint device nodes
+- ver-gpios: GPIO list to read the hardware version from
+- var-gpios: GPIO list to read the hardware variant information from
+- reset-gpios: GPIO list for the board's reset GPIOs
+
+Example:
+
+
+board {
+ compatible = "gdsys,board_gazerbeam";
+ csb = <&board_soc>;
+ serdes = <&SERDES>;
+ rxaui0 = <&RXAUI0>;
+ rxaui1 = <&RXAUI1>;
+ rxaui2 = <&RXAUI2>;
+ rxaui3 = <&RXAUI3>;
+ fpga0 = <&FPGA0>;
+ fpga1 = <&FPGA1>;
+ ioep0 = <&IOEP0>;
+ ioep1 = <&IOEP1>;
+
+ ver-gpios = <&PPCPCA 12 0
+ &PPCPCA 13 0
+ &PPCPCA 14 0
+ &PPCPCA 15 0>;
+
+ /* MC2/SC-Board */
+ var-gpios-mc2 = <&GPIO_VB0 0 0 /* VAR-MC_SC */
+ &GPIO_VB0 11 0>; /* VAR-CON */
+ /* MC4-Board */
+ var-gpios-mc4 = <&GPIO_VB1 0 0 /* VAR-MC_SC */
+ &GPIO_VB1 11 0>; /* VAR-CON */
+
+ reset-gpios = <&gpio0 1 0 &gpio0 2 1>;
+};
diff --git a/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
new file mode 100644
index 0000000000..8313da8507
--- /dev/null
+++ b/doc/device-tree-bindings/clock/fsl,mpc83xx-clk.txt
@@ -0,0 +1,23 @@
+MPC83xx system clock devices
+
+MPC83xx SoCs supply a variety of clocks to drive various components of a
+system.
+
+Required properties:
+- compatible: must be one of "fsl,mpc8308-clk",
+ "fsl,mpc8309-clk",
+ "fsl,mpc8313-clk",
+ "fsl,mpc8315-clk",
+ "fsl,mpc832x-clk",
+ "fsl,mpc8349-clk",
+ "fsl,mpc8360-clk",
+ "fsl,mpc8379-clk"
+ depending on which SoC is employed
+- #clock-cells: Must be 1
+
+Example:
+
+socclocks: clocks {
+ compatible = "fsl,mpc832x-clk";
+ #clock-cells = <1>;
+};
diff --git a/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
new file mode 100644
index 0000000000..ac563d906a
--- /dev/null
+++ b/doc/device-tree-bindings/cpu/fsl,mpc83xx.txt
@@ -0,0 +1,34 @@
+MPC83xx CPU devices
+
+MPC83xx SoCs contain a e300 core as their main processor.
+
+Required properties:
+- compatible: must be one of "fsl,mpc83xx",
+ "fsl,mpc8308",
+ "fsl,mpc8309",
+ "fsl,mpc8313",
+ "fsl,mpc8315",
+ "fsl,mpc832x",
+ "fsl,mpc8349",
+ "fsl,mpc8360",
+ "fsl,mpc8379"
+- clocks: has to have two entries, which must be the core clock at index 0 and
+ the CSB (Coherent System Bus) clock at index 1. Both are given by a suitable
+ "fsl,mpc83xx-clk" device
+
+Example:
+
+socclocks: clocks {
+ compatible = "fsl,mpc8315-clk";
+ #clock-cells = <1>;
+};
+
+cpus {
+ compatible = "cpu_bus";
+
+ PowerPC,8315@0 {
+ compatible = "fsl,mpc8315";
+ clocks = <&socclocks MPC83XX_CLK_CORE
+ &socclocks MPC83XX_CLK_CSB>;
+ };
+};
diff --git a/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt b/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt
new file mode 100644
index 0000000000..64a9b5b154
--- /dev/null
+++ b/doc/device-tree-bindings/misc/misc/fsl,mpc83xx-serdes.txt
@@ -0,0 +1,24 @@
+MPC83xx SerDes controller devices
+
+MPC83xx SoCs contain a built-in SerDes controller that determines which
+protocols (SATA, PCI Express, SGMII, ...) are used on the system's serdes lines
+and how the lines are configured.
+
+Required properties:
+- compatible: must be "fsl,mpc83xx-serdes"
+- reg: must point to the serdes controller's register map
+- proto: selects for which protocol the serdes lines are configured. One of
+ "sata", "pex", "pex-x2", "sgmii"
+- serdes-clk: determines the frequency the serdes lines are configured for. One
+ of 100, 125, 150.
+- vdd: determines whether 1.0V core VDD is used or not
+
+Example:
+
+SERDES: serdes@e3000 {
+ reg = <0xe3000 0x200>;
+ compatible = "fsl,mpc83xx-serdes";
+ proto = "pex";
+ serdes-clk = <100>;
+ vdd;
+};
diff --git a/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt b/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt
new file mode 100644
index 0000000000..db2ff8ca12
--- /dev/null
+++ b/doc/device-tree-bindings/misc/misc/gdsys,io-endpoint.txt
@@ -0,0 +1,20 @@
+gdsys IO endpoint of IHS FPGA devices
+
+The IO endpoint of IHS FPGA devices is a packet-based transmission interface
+that allows interconnected gdsys devices to send and receive data over the
+FPGA's main ethernet connection.
+
+Required properties:
+- compatible: must be "gdsys,io-endpoint"
+- reg: describes the address and length of the endpoint's register map (within
+ the FPGA's register space)
+
+Example:
+
+fpga0_ep0 {
+ compatible = "gdsys,io-endpoint";
+ reg = <0x020 0x10
+ 0x320 0x10
+ 0x340 0x10
+ 0x360 0x10>;
+};
diff --git a/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt b/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt
new file mode 100644
index 0000000000..acd466fdc6
--- /dev/null
+++ b/doc/device-tree-bindings/misc/misc/gdsys,iocon_fpga.txt
@@ -0,0 +1,19 @@
+gdsys IHS FPGA for CON devices
+
+The gdsys IHS FPGA is the main FPGA on gdsys CON devices. This driver provides
+support for enabling and starting the FPGA, as well as verifying working bus
+communication.
+
+Required properties:
+- compatible: must be "gdsys,iocon_fpga"
+- reset-gpios: List of GPIOs controlling the FPGA's reset
+- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
+ done
+
+Example:
+
+FPGA0 {
+ compatible = "gdsys,iocon_fpga";
+ reset-gpios = <&PPCPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+};
diff --git a/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt b/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt
new file mode 100644
index 0000000000..819db22bf7
--- /dev/null
+++ b/doc/device-tree-bindings/misc/misc/gdsys,iocpu_fpga.txt
@@ -0,0 +1,19 @@
+gdsys IHS FPGA for CPU devices
+
+The gdsys IHS FPGA is the main FPGA on gdsys CPU devices. This driver provides
+support for enabling and starting the FPGA, as well as verifying working bus
+communication.
+
+Required properties:
+- compatible: must be "gdsys,iocpu_fpga"
+- reset-gpios: List of GPIOs controlling the FPGA's reset
+- done-gpios: List of GPIOs notifying whether the FPGA's reconfiguration is
+ done
+
+Example:
+
+FPGA0 {
+ compatible = "gdsys,iocpu_fpga";
+ reset-gpios = <&PPCPCA 26 0>;
+ done-gpios = <&GPIO_VB0 19 0>;
+};
diff --git a/doc/device-tree-bindings/misc/misc/gdsys,soc.txt b/doc/device-tree-bindings/misc/misc/gdsys,soc.txt
new file mode 100644
index 0000000000..278e935b16
--- /dev/null
+++ b/doc/device-tree-bindings/misc/misc/gdsys,soc.txt
@@ -0,0 +1,16 @@
+gdsys soc bus driver
+
+This driver provides a simple interface for the busses associated with gdsys
+IHS FPGAs. The bus itself contains devices whose register maps are contained
+within the FPGA's register space.
+
+Required properties:
+- fpga: A phandle to the controlling IHS FPGA
+
+Example:
+
+FPGA0BUS: fpga0bus {
+ compatible = "gdsys,soc";
+ ranges = <0x0 0xe0600000 0x00004000>;
+ fpga = <&FPGA0>;
+};
diff --git a/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt b/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt
new file mode 100644
index 0000000000..da01fe908d
--- /dev/null
+++ b/doc/device-tree-bindings/ram/fsl,mpc83xx-mem-controller.txt
@@ -0,0 +1,314 @@
+MPC83xx RAM controller
+
+This driver supplies support for the embedded RAM controller on MCP83xx-series
+SoCs.
+
+For static configuration mode, each controller node should have child nodes
+describing the actual RAM modules installed.
+
+Controller node
+===============
+
+Required properties:
+- compatible: Must be "fsl,mpc83xx-mem-controller"
+- reg: The address of the RAM controller's register space
+- #address-cells: Must be 2
+- #size-cells: Must be 1
+- driver_software_override: DDR driver software override is enabled (1) or
+ disabled (0)
+- p_impedance_override: DDR driver software p-impedance override; possible
+ values:
+ * DSO_P_IMPEDANCE_HIGHEST_Z
+ * DSO_P_IMPEDANCE_MUCH_HIGHER_Z
+ * DSO_P_IMPEDANCE_HIGHER_Z
+ * DSO_P_IMPEDANCE_NOMINAL
+ * DSO_P_IMPEDANCE_LOWER_Z
+- n_impedance_override: DDR driver software n-impedance override; possible
+ values:
+ * DSO_N_IMPEDANCE_HIGHEST_Z
+ * DSO_N_IMPEDANCE_MUCH_HIGHER_Z
+ * DSO_N_IMPEDANCE_HIGHER_Z
+ * DSO_N_IMPEDANCE_NOMINAL
+ * DSO_N_IMPEDANCE_LOWER_Z
+- odt_termination_value: ODT termination value for I/Os; possible values:
+ * ODT_TERMINATION_75_OHM
+ * ODT_TERMINATION_150_OHM
+- ddr_type: Selects voltage level for DDR pads; possible
+ values:
+ * DDR_TYPE_DDR2_1_8_VOLT
+ * DDR_TYPE_DDR1_2_5_VOLT
+- mvref_sel: Determine where MVREF_SEL signal is generated;
+ possible values:
+ * MVREF_SEL_EXTERNAL
+ * MVREF_SEL_INTERNAL_GVDD
+- m_odr: Disable memory transaction reordering; possible
+ values:
+ * M_ODR_ENABLE
+ * M_ODR_DISABLE
+- clock_adjust: Clock adjust; possible values:
+ * CLOCK_ADJUST_025
+ * CLOCK_ADJUST_05
+ * CLOCK_ADJUST_075
+ * CLOCK_ADJUST_1
+- ext_refresh_rec: Extended refresh recovery time; possible values:
+ 0, 16, 32, 48, 64, 80, 96, 112
+- read_to_write: Read-to-write turnaround; possible values:
+ 0, 1, 2, 3
+- write_to_read: Write-to-read turnaround; possible values:
+ 0, 1, 2, 3
+- read_to_read: Read-to-read turnaround; possible values:
+ 0, 1, 2, 3
+- write_to_write: Write-to-write turnaround; possible values:
+ 0, 1, 2, 3
+- active_powerdown_exit: Active powerdown exit timing; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- precharge_powerdown_exit: Precharge powerdown exit timing; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- odt_powerdown_exit: ODT powerdown exit timing; possible values:
+ 0, 1, 2, 3, 4, 5, 6, 7, 8,
+ 9, 10, 11, 12, 13, 14, 15
+- mode_reg_set_cycle: Mode register set cycle time; possible values:
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15
+- precharge_to_activate: Precharge-to-acitvate interval; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- activate_to_precharge: Activate to precharge interval; possible values:
+ 4, 5, 6, 7, 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19
+- activate_to_readwrite: Activate to read/write interval for SDRAM;
+ possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- mcas_latency: MCAS latency from READ command; possible values:
+ * CASLAT_20
+ * CASLAT_25
+ * CASLAT_30
+ * CASLAT_35
+ * CASLAT_40
+ * CASLAT_45
+ * CASLAT_50
+ * CASLAT_55
+ * CASLAT_60
+ * CASLAT_65
+ * CASLAT_70
+ * CASLAT_75
+ * CASLAT_80
+- refresh_recovery: Refresh recovery time; possible values:
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23
+- last_data_to_precharge: Last data to precharge minimum interval; possible
+ values:
+ 1, 2, 3, 4, 5, 6, 7
+- activate_to_activate: Activate-to-activate interval; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- last_write_data_to_read: Last write data pair to read command issue
+ interval; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- additive_latency: Additive latency; possible values:
+ 0, 1, 2, 3, 4, 5
+- mcas_to_preamble_override: MCAS-to-preamble-override; possible values:
+ * READ_LAT
+ * READ_LAT_PLUS_1_4
+ * READ_LAT_PLUS_1_2
+ * READ_LAT_PLUS_3_4
+ * READ_LAT_PLUS_1
+ * READ_LAT_PLUS_5_4
+ * READ_LAT_PLUS_3_2
+ * READ_LAT_PLUS_7_4
+ * READ_LAT_PLUS_2
+ * READ_LAT_PLUS_9_4
+ * READ_LAT_PLUS_5_2
+ * READ_LAT_PLUS_11_4
+ * READ_LAT_PLUS_3
+ * READ_LAT_PLUS_13_4
+ * READ_LAT_PLUS_7_2
+ * READ_LAT_PLUS_15_4
+ * READ_LAT_PLUS_4
+ * READ_LAT_PLUS_17_4
+ * READ_LAT_PLUS_9_2
+ * READ_LAT_PLUS_19_4
+- write_latency: Write latency; possible values:
+ 1, 2, 3, 4, 5, 6, 7
+- read_to_precharge: Read to precharge; possible values:
+ 1, 2, 3, 4
+- write_cmd_to_write_data: Write command to write data strobe timing
+ adjustment; possible values:
+ * CLOCK_DELAY_0
+ * CLOCK_DELAY_1_4
+ * CLOCK_DELAY_1_2
+ * CLOCK_DELAY_3_4
+ * CLOCK_DELAY_1
+ * CLOCK_DELAY_5_4
+ * CLOCK_DELAY_3_2
+- minimum_cke_pulse_width: Minimum CKE pulse width; possible values:
+ 1, 2, 3, 4
+- four_activates_window: Window for four activates; possible values:
+ 1, 2, 3, 4 8, 9, 10, 11, 12,
+ 13, 14, 15, 16, 17, 18, 19
+- self_refresh: Self refresh (during sleep); possible values:
+ * SREN_DISABLE
+ * SREN_ENABLE
+- ecc: Support for ECC; possible values:
+ * ECC_DISABLE
+ * ECC_ENABLE
+- registered_dram: Support for registered DRAM; possible values:
+ * RD_DISABLE
+ * RD_ENABLE
+- sdram_type: Type of SDRAM device to be used; possible values:
+ * TYPE_DDR1
+ * TYPE_DDR2
+- dynamic_power_management: Dynamic power management mode; possible values:
+ * DYN_PWR_DISABLE
+ * DYN_PWR_ENABLE
+- databus_width: DRAM data bus width; possible values
+ * DATA_BUS_WIDTH_16
+ * DATA_BUS_WIDTH_32
+- nc_auto_precharge: Non-concurrent auto-precharge; possible values:
+ * NCAP_DISABLE
+ * NCAP_ENABLE
+- timing_2t: 2T timing; possible values:
+ * TIMING_1T
+ * TIMING_2T
+- bank_interleaving_ctrl: Bank (chip select) interleaving control; possible
+ values:
+ * INTERLEAVE_NONE
+ * INTERLEAVE_1_AND_2
+- precharge_bit_8: Precharge bin 8; possible values
+ * PRECHARGE_MA_10
+ * PRECHARGE_MA_8
+- half_strength: Global half-strength override; possible values:
+ * STRENGTH_FULL
+ * STRENGTH_HALF
+- bypass_initialization: Bypass initialization; possible values:
+ * INITIALIZATION_DONT_BYPASS
+ * INITIALIZATION_BYPASS
+- force_self_refresh: Force self refresh; possible values:
+ * MODE_NORMAL
+ * MODE_REFRESH
+- dll_reset: DLL reset; possible values:
+ * DLL_RESET_ENABLE
+ * DLL_RESET_DISABLE
+- dqs_config: DQS configuration; possible values:
+ * DQS_TRUE
+- odt_config: ODT configuration; possible values:
+ * ODT_ASSERT_NEVER
+ * ODT_ASSERT_WRITES
+ * ODT_ASSERT_READS
+ * ODT_ASSERT_ALWAYS
+- posted_refreshes: Number of posted refreshes
+ 1, 2, 3, 4, 5, 6, 7, 8
+- sdmode: Initial value loaded into the DDR SDRAM mode
+ register
+- esdmode: Initial value loaded into the DDR SDRAM extended
+ mode register
+- esdmode2: Initial value loaded into the DDR SDRAM extended
+ mode 2 register
+- esdmode3: Initial value loaded into the DDR SDRAM extended
+ mode 3 register
+- refresh_interval: Refresh interval; possible values:
+ 0 - 65535
+- precharge_interval: Precharge interval; possible values:
+ 0 - 16383
+
+RAM module node:
+================
+
+Required properties:
+- reg: A triple <cs addr size>, which consists of:
+ * cs - the chipselect used to drive this RAM module
+ * addr - the address where this RAM module's memory is map
+ to in the global memory space
+ * size - the size of the RAM module's memory in bytes
+- auto_precharge: Chip select auto-precharge; possible values:
+ * AUTO_PRECHARGE_ENABLE
+ * AUTO_PRECHARGE_DISABLE
+- odt_rd_cfg: ODT for reads configuration; possible values:
+ * ODT_RD_NEVER
+ * ODT_RD_ONLY_CURRENT
+ * ODT_RD_ONLY_OTHER_CS
+ * ODT_RD_ONLY_OTHER_DIMM
+ * ODT_RD_ALL
+- odt_wr_cfg: ODT for writes configuration; possible values:
+ * ODT_WR_NEVER
+ * ODT_WR_ONLY_CURRENT
+ * ODT_WR_ONLY_OTHER_CS
+ * ODT_WR_ONLY_OTHER_DIMM
+ * ODT_WR_ALL
+- bank_bits: Number of bank bits for SDRAM on chip select; possible
+ values:
+ 2, 3
+- row_bits: Number of row bits for SDRAM on chip select; possible values:
+ 12, 13, 14
+- col_bits: Number of column bits for SDRAM on chip select; possible
+ values:
+ 8, 9, 10, 11
+
+Example:
+
+memory@2000 {
+ #address-cells = <2>;
+ #size-cells = <1>;
+ compatible = "fsl,mpc83xx-mem-controller";
+ reg = <0x2000 0x1000>;
+ device_type = "memory";
+ u-boot,dm-pre-reloc;
+
+ driver_software_override = <DSO_ENABLE>;
+ p_impedance_override = <DSO_P_IMPEDANCE_NOMINAL>;
+ n_impedance_override = <DSO_N_IMPEDANCE_NOMINAL>;
+ odt_termination_value = <ODT_TERMINATION_150_OHM>;
+ ddr_type = <DDR_TYPE_DDR2_1_8_VOLT>;
+
+ clock_adjust = <CLOCK_ADJUST_05>;
+
+ read_to_write = <0>;
+ write_to_read = <0>;
+ read_to_read = <0>;
+ write_to_write = <0>;
+ active_powerdown_exit = <2>;
+ precharge_powerdown_exit = <6>;
+ odt_powerdown_exit = <8>;
+ mode_reg_set_cycle = <2>;
+
+ precharge_to_activate = <2>;
+ activate_to_precharge = <6>;
+ activate_to_readwrite = <2>;
+ mcas_latency = <CASLAT_40>;
+ refresh_recovery = <17>;
+ last_data_to_precharge = <2>;
+ activate_to_activate = <2>;
+ last_write_data_to_read = <2>;
+
+ additive_latency = <0>;
+ mcas_to_preamble_override = <READ_LAT_PLUS_1_2>;
+ write_latency = <3>;
+ read_to_precharge = <2>;
+ write_cmd_to_write_data = <CLOCK_DELAY_1_2>;
+ minimum_cke_pulse_width = <3>;
+ four_activates_window = <5>;
+
+ self_refresh = <SREN_ENABLE>;
+ sdram_type = <TYPE_DDR2>;
+ databus_width = <DATA_BUS_WIDTH_32>;
+
+ force_self_refresh = <MODE_NORMAL>;
+ dll_reset = <DLL_RESET_ENABLE>;
+ dqs_config = <DQS_TRUE>;
+ odt_config = <ODT_ASSERT_READS>;
+ posted_refreshes = <1>;
+
+ refresh_interval = <2084>;
+ precharge_interval = <256>;
+
+ sdmode = <0x0242>;
+ esdmode = <0x0440>;
+
+ ram@0 {
+ reg = <0x0 0x0 0x8000000>;
+ compatible = "nanya,nt5tu64m16hg";
+
+ odt_rd_cfg = <ODT_RD_NEVER>;
+ odt_wr_cfg = <ODT_WR_ONLY_CURRENT>;
+ bank_bits = <3>;
+ row_bits = <13>;
+ col_bits = <10>;
+ };
+};
diff --git a/doc/device-tree-bindings/reserved-memory/reserved-memory.txt b/doc/device-tree-bindings/reserved-memory/reserved-memory.txt
new file mode 100644
index 0000000000..bac4afa3b1
--- /dev/null
+++ b/doc/device-tree-bindings/reserved-memory/reserved-memory.txt
@@ -0,0 +1,136 @@
+*** Reserved memory regions ***
+
+Reserved memory is specified as a node under the /reserved-memory node.
+The operating system shall exclude reserved memory from normal usage
+one can create child nodes describing particular reserved (excluded from
+normal use) memory regions. Such memory regions are usually designed for
+the special usage by various device drivers.
+
+Parameters for each memory region can be encoded into the device tree
+with the following nodes:
+
+/reserved-memory node
+---------------------
+#address-cells, #size-cells (required) - standard definition
+ - Should use the same values as the root node
+ranges (required) - standard definition
+ - Should be empty
+
+/reserved-memory/ child nodes
+-----------------------------
+Each child of the reserved-memory node specifies one or more regions of
+reserved memory. Each child node may either use a 'reg' property to
+specify a specific range of reserved memory, or a 'size' property with
+optional constraints to request a dynamically allocated block of memory.
+
+Following the generic-names recommended practice, node names should
+reflect the purpose of the node (ie. "framebuffer" or "dma-pool"). Unit
+address (@<address>) should be appended to the name if the node is a
+static allocation.
+
+Properties:
+Requires either a) or b) below.
+a) static allocation
+ reg (required) - standard definition
+b) dynamic allocation
+ size (required) - length based on parent's #size-cells
+ - Size in bytes of memory to reserve.
+ alignment (optional) - length based on parent's #size-cells
+ - Address boundary for alignment of allocation.
+ alloc-ranges (optional) - prop-encoded-array (address, length pairs).
+ - Specifies regions of memory that are
+ acceptable to allocate from.
+
+If both reg and size are present, then the reg property takes precedence
+and size is ignored.
+
+Additional properties:
+compatible (optional) - standard definition
+ - may contain the following strings:
+ - shared-dma-pool: This indicates a region of memory meant to be
+ used as a shared pool of DMA buffers for a set of devices. It can
+ be used by an operating system to instantiate the necessary pool
+ management subsystem if necessary.
+ - vendor specific string in the form <vendor>,[<device>-]<usage>
+no-map (optional) - empty property
+ - Indicates the operating system must not create a virtual mapping
+ of the region as part of its standard mapping of system memory,
+ nor permit speculative access to it under any circumstances other
+ than under the control of the device driver using the region.
+reusable (optional) - empty property
+ - The operating system can use the memory in this region with the
+ limitation that the device driver(s) owning the region need to be
+ able to reclaim it back. Typically that means that the operating
+ system can use that region to store volatile or cached data that
+ can be otherwise regenerated or migrated elsewhere.
+
+Linux implementation note:
+- If a "linux,cma-default" property is present, then Linux will use the
+ region for the default pool of the contiguous memory allocator.
+
+- If a "linux,dma-default" property is present, then Linux will use the
+ region for the default pool of the consistent DMA allocator.
+
+Device node references to reserved memory
+-----------------------------------------
+Regions in the /reserved-memory node may be referenced by other device
+nodes by adding a memory-region property to the device node.
+
+memory-region (optional) - phandle, specifier pairs to children of /reserved-memory
+
+Example
+-------
+This example defines 3 contiguous regions are defined for Linux kernel:
+one default of all device drivers (named linux,cma@72000000 and 64MiB in size),
+one dedicated to the framebuffer device (named framebuffer@78000000, 8MiB), and
+one for multimedia processing (named multimedia-memory@77000000, 64MiB).
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ memory {
+ reg = <0x40000000 0x40000000>;
+ };
+
+ reserved-memory {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+
+ /* global autoconfigured region for contiguous allocations */
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x4000000>;
+ alignment = <0x2000>;
+ linux,cma-default;
+ };
+
+ display_reserved: framebuffer@78000000 {
+ reg = <0x78000000 0x800000>;
+ };
+
+ multimedia_reserved: multimedia@77000000 {
+ compatible = "acme,multimedia-memory";
+ reg = <0x77000000 0x4000000>;
+ };
+ };
+
+ /* ... */
+
+ fb0: video@12300000 {
+ memory-region = <&display_reserved>;
+ /* ... */
+ };
+
+ scaler: scaler@12500000 {
+ memory-region = <&multimedia_reserved>;
+ /* ... */
+ };
+
+ codec: codec@12600000 {
+ memory-region = <&multimedia_reserved>;
+ /* ... */
+ };
+};
diff --git a/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt b/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt
new file mode 100644
index 0000000000..608d24110b
--- /dev/null
+++ b/doc/device-tree-bindings/timer/fsl,mpc83xx-timer.txt
@@ -0,0 +1,21 @@
+MPC83xx timer devices
+
+MPC83xx SoCs offer a decrementer interrupt that can be used to implement delay
+functionality, and periodically triggered actions.
+
+Required properties:
+- compatible: must be "fsl,mpc83xx-timer"
+- clocks: must be a reference to the system's CSB (coherent system bus) clock,
+ provided by one of the "fsl,mpc83xx-clk" devices
+
+Example:
+
+socclocks: clocks {
+ compatible = "fsl,mpc832x-clk";
+ #clock-cells = <1>;
+};
+
+timer {
+ compatible = "fsl,mpc83xx-timer";
+ clocks = <&socclocks MPC83XX_CLK_CSB>;
+};