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authorNishanth Menon <nm@ti.com>2023-07-27 21:58:45 +0300
committerHeinrich Schuchardt <heinrich.schuchardt@canonical.com>2023-07-28 12:36:37 +0300
commit68b3baaf3b3eb943cbb8363a064669527df3c79e (patch)
tree38a36fba500808c224be2d5b01bf5f7e19836224 /doc
parentcce3e7a23db49b29fe64572323a335329406ea67 (diff)
downloadu-boot-68b3baaf3b3eb943cbb8363a064669527df3c79e.tar.xz
doc: board: ti: am62x/j7200: Update with common boot flow diagram
Update the bootflow svg diagram and reuse across the platforms as they are common. Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/board/ti/am62x_sk.rst68
-rw-r--r--doc/board/ti/img/boot_diagram_k3_current.svg1925
-rw-r--r--doc/board/ti/j7200_evm.rst85
3 files changed, 1927 insertions, 151 deletions
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst
index 0a3bbdfaf0..dd697e7091 100644
--- a/doc/board/ti/am62x_sk.rst
+++ b/doc/board/ti/am62x_sk.rst
@@ -42,73 +42,7 @@ Boot Flow:
----------
Below is the pictorial representation of boot flow:
-.. code-block:: text
-
- +------------------------------------------------------------------------+
- | TIFS | Main R5 | A53 |
- +------------------------------------------------------------------------+
- | +--------+ | | |
- | | Reset | | | |
- | +--------+ | | |
- | : | | |
- | +--------+ | +-----------+ | |
- | | *ROM* |----------|-->| Reset rls | | |
- | +--------+ | +-----------+ | |
- | | | | : | |
- | | ROM | | : | |
- | |services| | : | |
- | | | | +-------------+ | |
- | | | | | *R5 ROM* | | |
- | | | | +-------------+ | |
- | | |<---------|---|Load and auth| | |
- | | | | | tiboot3.bin | | |
- | +--------+ | +-------------+ | |
- | | |<---------|---| Load sysfw | | |
- | | | | | part to TIFS| | |
- | | | | | core | | |
- | | | | +-------------+ | |
- | | | | : | |
- | | | | : | |
- | | | | : | |
- | | | | +-------------+ | |
- | | | | | *R5 SPL* | | |
- | | | | +-------------+ | |
- | | | | | DDR | | |
- | | | | | config | | |
- | | | | +-------------+ | |
- | | | | | Load | | |
- | | | | | tispl.bin | | |
- | | | | +-------------+ | |
- | | | | | Load R5 | | |
- | | | | | firmware | | |
- | | | | +-------------+ | |
- | | |<---------|---| Start A53 | | |
- | | | | | and jump to | | |
- | | | | | DM fw image | | |
- | | | | +-------------+ | |
- | | | | | +-----------+ |
- | | |----------|-----------------------|---->| Reset rls | |
- | | | | | +-----------+ |
- | | TIFS | | | : |
- | |Services| | | +-------------+ |
- | | |<---------|-----------------------|---->|*TF-A/OP-TEE*| |
- | | | | | +-------------+ |
- | | | | | : |
- | | | | | +-----------+ |
- | | |<---------|-----------------------|---->| *A53 SPL* | |
- | | | | | +-----------+ |
- | | | | | | Load | |
- | | | | | | u-boot.img| |
- | | | | | +-----------+ |
- | | | | | : |
- | | | | | +-----------+ |
- | | |<---------|-----------------------|---->| *U-Boot* | |
- | | | | | +-----------+ |
- | | | | | | prompt | |
- | | |----------|-----------------------|-----+-----------+-----|
- | +--------+ | | |
- | | | |
- +------------------------------------------------------------------------+
+.. image:: img/boot_diagram_k3_current.svg
- Here TIFS acts as master and provides all the critical services. R5/A53
requests TIFS to get these services done as shown in the above diagram.
diff --git a/doc/board/ti/img/boot_diagram_k3_current.svg b/doc/board/ti/img/boot_diagram_k3_current.svg
new file mode 100644
index 0000000000..995afd890e
--- /dev/null
+++ b/doc/board/ti/img/boot_diagram_k3_current.svg
@@ -0,0 +1,1925 @@
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diff --git a/doc/board/ti/j7200_evm.rst b/doc/board/ti/j7200_evm.rst
index 24d309a9ff..5c980bcace 100644
--- a/doc/board/ti/j7200_evm.rst
+++ b/doc/board/ti/j7200_evm.rst
@@ -30,90 +30,7 @@ Boot Flow:
----------
Below is the pictorial representation of boot flow:
-.. code-block:: text
-
- +------------------------------------------------------------------------+-----------------------+
- | DMSC | MCU R5 | A72 | MAIN R5/C7x |
- +------------------------------------------------------------------------+-----------------------+
- | +--------+ | | | |
- | | Reset | | | | |
- | +--------+ | | | |
- | : | | | |
- | +--------+ | +-----------+ | | |
- | | *ROM* |----------|-->| Reset rls | | | |
- | +--------+ | +-----------+ | | |
- | | | | : | | |
- | | ROM | | : | | |
- | |services| | : | | |
- | | | | +-------------+ | | |
- | | | | | *R5 ROM* | | | |
- | | | | +-------------+ | | |
- | | |<---------|---|Load and auth| | | |
- | | | | | tiboot3.bin | | | |
- | | Start | | +-------------+ | | |
- | | TIFS |<---------|---| Start | | | |
- | | | | | TIFS | | | |
- | +--------+ | +-------------+ | | |
- | : | | | | | |
- | +---------+ | | Load | | | |
- | | *TIFS* | | | system | | | |
- | +---------+ | | Config data | | | |
- | | |<--------|---| | | | |
- | | | | +-------------+ | | |
- | | | | : | | |
- | | | | : | | |
- | | | | : | | |
- | | | | +-------------+ | | |
- | | | | | *R5 SPL* | | | |
- | | | | +-------------+ | | |
- | | | | | DDR | | | |
- | | | | | config | | | |
- | | | | +-------------+ | | |
- | | | | | Load | | | |
- | | | | | tispl.bin | | | |
- | | | | +-------------+ | | |
- | | | | | Load R5 | | | |
- | | | | | firmware | | | |
- | | | | +-------------+ | | |
- | | |<--------|---| Start A72 | | | |
- | | | | | and jump to | | | |
- | | | | | DM fw image | | | |
- | | | | +-------------+ | | |
- | | | | | +-----------+ | |
- | | |---------|-----------------------|---->| Reset rls | | |
- | | | | | +-----------+ | |
- | | TIFS | | | : | |
- | |Services | | | +-------------+ | |
- | | |<--------|-----------------------|---->|*TF-A/OP-TEE*| | |
- | | | | | +-------------+ | |
- | | | | | : | |
- | | | | | +-----------+ | |
- | | |<--------|-----------------------|---->| *A72 SPL* | | |
- | | | | | +-----------+ | |
- | | | | | | Load | | |
- | | | | | | u-boot.img| | |
- | | | | | +-----------+ | |
- | | | | | : | |
- | | | | | +-----------+ | |
- | | |<--------|-----------------------|---->| *U-Boot* | | |
- | | | | | +-----------+ | |
- | | | | | | prompt | | |
- | | | | | +-----------+ | |
- | | | | | | Load R5 | | |
- | | | | | | Firmware | | |
- | | | | | +-----------+ | |
- | | |<--------|-----------------------|-----| Start R5 | | +-----------+ |
- | | |---------|-----------------------|-----+-----------+-----|----->| R5 starts | |
- | | | | | | Load C7 | | +-----------+ |
- | | | | | | Firmware | | |
- | | | | | +-----------+ | |
- | | |<--------|-----------------------|-----| Start C7 | | +-----------+ |
- | | |---------|-----------------------|-----+-----------+-----|----->| C7 starts | |
- | | | | | | +-----------+ |
- | | | | | | |
- | +---------+ | | | |
- | | | | |
- +------------------------------------------------------------------------+-----------------------+
+.. image:: img/boot_diagram_k3_current.svg
- Here DMSC acts as master and provides all the critical services. R5/A72
requests DMSC to get these services done as shown in the above diagram.