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author | Tom Rini <trini@konsulko.com> | 2021-01-06 15:57:33 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2021-01-06 15:57:33 +0300 |
commit | bc0b99bd8b19599f670f42401de655fa9b44cd94 (patch) | |
tree | 8f5294dc16657c32b1a401c13a1f2a0579ac62e2 /doc | |
parent | b11f634b1c1be6ab419758c6596c673445e5ac70 (diff) | |
parent | 0109db1cd1e63b35c1c84d6bc2ccaa26aa6b7ce3 (diff) | |
download | u-boot-bc0b99bd8b19599f670f42401de655fa9b44cd94.tar.xz |
Merge tag 'xilinx-for-v2021.04' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.04
arm64:
- DT updates
microblaze:
- Add support for NOR device support
spi:
- Fix unaligned data write issue
nand:
- Minor code change
xilinx:
- Fru fix in limit calculation
- Fill git repo link for all Xilinx boards
video:
- Add support for seps525 spi display
tools:
- Minor Vitis file support
cmd/common
- Minor code indentation fixes
serial:
- Uartlite debug uart initialization fix
Diffstat (limited to 'doc')
-rw-r--r-- | doc/device-tree-bindings/video/syncoam,seps525.txt | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/video/syncoam,seps525.txt b/doc/device-tree-bindings/video/syncoam,seps525.txt new file mode 100644 index 0000000000..e1e0db9d71 --- /dev/null +++ b/doc/device-tree-bindings/video/syncoam,seps525.txt @@ -0,0 +1,24 @@ +spi based seps525 framebuffer display driver + +Driver for seps525 display controller (in spi mode), This binding supports selection +of spi chipselect, spi max frequency, gpio to drive dc and reset pin of seps525 +controller and spi transaction bit length. + +Required properties: +- compatible: "syncoam,seps525" +- reg: Specifies the chip-select the seps525 is connected to on the spi bus +- reset-gpios: gpio connected to reset pin of seps525 controller. +- dc-gpios: gpio connected to dc pin of seps525 controller: +- buswidth: bitlength of each spi transaction + +Example: + displayspi@0 { + compatible = "syncoam,seps525"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-cpol; + spi-cpha; + buswidth = <8>; + reset-gpios = <&gpio 0x1c GPIO_ACTIVE_LOW>; + dc-gpios = <&gpio 0x1b GPIO_ACTIVE_HIGH>; + }; |