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authorPatrick Delaunay <patrick.delaunay@st.com>2020-05-25 13:19:44 +0300
committerPatrick Delaunay <patrick.delaunay@st.com>2020-07-07 17:01:23 +0300
commit37ad8377af00128adc47fb1192142ac9dfbf1f9d (patch)
tree99298fd93ebb907fe3d7f24587b8b88aa9f1cbed /doc
parent918e9c3d638722e5169091594846462e7af69f47 (diff)
downloadu-boot-37ad8377af00128adc47fb1192142ac9dfbf1f9d.tar.xz
stm32mp1: clk: configure pll1 with OPP
The PLL1 node (st,pll1) is optional in device tree, the max supported frequency define in OPP node is used when the node is absent. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
Diffstat (limited to 'doc')
-rw-r--r--doc/device-tree-bindings/clock/st,stm32mp1.txt4
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/device-tree-bindings/clock/st,stm32mp1.txt b/doc/device-tree-bindings/clock/st,stm32mp1.txt
index a3d427911d..4d4136d2fc 100644
--- a/doc/device-tree-bindings/clock/st,stm32mp1.txt
+++ b/doc/device-tree-bindings/clock/st,stm32mp1.txt
@@ -87,6 +87,10 @@ Optional Properties:
are listed with associated reg 0 to 3.
PLLx is off when the associated node is absent or deactivated.
+ For PLL1, when the node is absent, the frequency of the OPP node is used
+ to compute the PLL setting (see compatible "operating-points-v2" in
+ opp/opp.txt for details).
+
Here are the available properties for each PLL node:
- compatible: should be "st,stm32mp1-pll"