diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2020-04-17 09:45:35 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-04-24 23:40:09 +0300 |
| commit | f62782fb2999dd8109a3ffe9ee0a51e54ab034ab (patch) | |
| tree | d14f6669d89c38b5d584b6b57e95bf6e38862448 /drivers/cache | |
| parent | a3d7cb1939ada77a2c0b7668bb9d80298de3ff31 (diff) | |
| download | u-boot-f62782fb2999dd8109a3ffe9ee0a51e54ab034ab.tar.xz | |
cache: l2x0: Fix write to incorrect shared-override bit
The existing code write bit-0 for shared attribute override enable bit.
It should be bit-22 based on cache controller specification [1].
[1] http://infocenter.arm.com/help/topic/com.arm.doc.ddi0246f/DDI0246F_l2c310_r3p2_trm.pdf
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Diffstat (limited to 'drivers/cache')
| -rw-r--r-- | drivers/cache/cache-l2x0.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/cache/cache-l2x0.c b/drivers/cache/cache-l2x0.c index 67c752d076..226824c283 100644 --- a/drivers/cache/cache-l2x0.c +++ b/drivers/cache/cache-l2x0.c @@ -33,8 +33,8 @@ static void l2c310_of_parse_and_init(struct udevice *dev) saved_reg &= ~L310_AUX_CTRL_INST_PREFETCH_MASK; } - saved_reg |= dev_read_bool(dev, "arm,shared-override"); - writel(saved_reg, ®s->pl310_aux_ctrl); + if (dev_read_bool(dev, "arm,shared-override")) + saved_reg |= L310_SHARED_ATT_OVERRIDE_ENABLE; saved_reg = readl(®s->pl310_tag_latency_ctrl); if (!dev_read_u32_array(dev, "arm,tag-latency", tag, 3)) |