diff options
| author | Patrice Chotard <patrice.chotard@st.com> | 2017-11-15 15:14:51 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2017-11-30 06:30:50 +0300 |
| commit | 928954fe58e69767b138816ab58e1a7e48f2c685 (patch) | |
| tree | fbb0d14fa098f83ce19f7a17d0b67dae1423d61c /drivers/clk/clk_stm32f.c | |
| parent | fe8d4780fffb0fe211fda3a5253f154c1e026939 (diff) | |
| download | u-boot-928954fe58e69767b138816ab58e1a7e48f2c685.tar.xz | |
dm: misc: bind STM32F4/F7 clock from rcc MFD driver
Like STM32H7, now STM32F4/F7 clock drivers are binded by
MFD stm32_rcc driver.
This also allows to add reset support to STM32F4/F7 SoCs family.
As Reset driver is not part of SPL supported drivers, don't bind it
in case of SPL to avoid that stm32_rcc_bind() returns an error.
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
Reviewed-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'drivers/clk/clk_stm32f.c')
| -rw-r--r-- | drivers/clk/clk_stm32f.c | 54 |
1 files changed, 13 insertions, 41 deletions
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index c7af7a1d8d..6e29c55e0a 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -8,6 +8,7 @@ #include <common.h> #include <clk-uclass.h> #include <dm.h> +#include <stm32_rcc.h> #include <asm/io.h> #include <asm/arch/stm32.h> @@ -71,38 +72,6 @@ */ #define RCC_APB2ENR_SYSCFGEN BIT(14) - -struct pll_psc { - u8 pll_m; - u16 pll_n; - u8 pll_p; - u8 pll_q; - u8 ahb_psc; - u8 apb1_psc; - u8 apb2_psc; -}; - -#define AHB_PSC_1 0 -#define AHB_PSC_2 0x8 -#define AHB_PSC_4 0x9 -#define AHB_PSC_8 0xA -#define AHB_PSC_16 0xB -#define AHB_PSC_64 0xC -#define AHB_PSC_128 0xD -#define AHB_PSC_256 0xE -#define AHB_PSC_512 0xF - -#define APB_PSC_1 0 -#define APB_PSC_2 0x4 -#define APB_PSC_4 0x5 -#define APB_PSC_8 0x6 -#define APB_PSC_16 0x7 - -struct stm32_clk_info { - struct pll_psc sys_pll_psc; - bool has_overdrive; -}; - struct stm32_clk_info stm32f4_clk_info = { /* 180 MHz */ .sys_pll_psc = { @@ -311,7 +280,17 @@ static int stm32_clk_probe(struct udevice *dev) return -EINVAL; priv->base = (struct stm32_rcc_regs *)addr; - priv->info = (struct stm32_clk_info *)dev_get_driver_data(dev); + + switch (dev_get_driver_data(dev)) { + case STM32F4: + priv->info = &stm32f4_clk_info; + break; + case STM32F7: + priv->info = &stm32f7_clk_info; + break; + default: + return -EINVAL; + } if (priv->info->has_overdrive) { err = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, @@ -353,16 +332,9 @@ static struct clk_ops stm32_clk_ops = { .get_rate = stm32_clk_get_rate, }; -static const struct udevice_id stm32_clk_ids[] = { - { .compatible = "st,stm32f42xx-rcc", .data = (ulong)&stm32f4_clk_info}, - { .compatible = "st,stm32f746-rcc", .data = (ulong)&stm32f7_clk_info}, - {} -}; - U_BOOT_DRIVER(stm32fx_clk) = { - .name = "stm32fx_clk", + .name = "stm32fx_rcc_clock", .id = UCLASS_CLK, - .of_match = stm32_clk_ids, .ops = &stm32_clk_ops, .probe = stm32_clk_probe, .priv_auto_alloc_size = sizeof(struct stm32_clk), |