diff options
| author | Hai Pham <hai.pham.ud@renesas.com> | 2023-03-01 00:37:02 +0300 |
|---|---|---|
| committer | Marek Vasut <marek.vasut+renesas@mailbox.org> | 2023-04-07 18:13:28 +0300 |
| commit | 53f27dda29913631c42af498e266e17442e44972 (patch) | |
| tree | 757f15f43feca52594128a4f3d015885092aff53 /drivers/clk/renesas/Kconfig | |
| parent | 0296ec364dddc24bc956e5828b342257603c1a9e (diff) | |
| download | u-boot-53f27dda29913631c42af498e266e17442e44972.tar.xz | |
clk: renesas: Add R8A779G0 V4H clock tables
Add clock tables for R8A779G0 V4H SoC from Linux next
commit 058f4df42121 ("Add linux-next specific files for 20230228")
There is an adjustment to the clock tables to make them easier suitable
for U-Boot, PLL2 is not treated as GEN4 PLL type PLL2_VAR, but rather a
plain PLL2. This should be sufficient until PLL2_VAR is implemented in
the clock core.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Sync with Linux next 20230228 . Update from CLK to CPG core driver
Treat PLL2 as non-PLL2_VAR for now]
Diffstat (limited to 'drivers/clk/renesas/Kconfig')
| -rw-r--r-- | drivers/clk/renesas/Kconfig | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index cf28aed7c4..45671c6925 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -137,3 +137,9 @@ config CLK_R8A779F0 depends on CLK_RCAR_GEN3 help Enable this to support the clocks on Renesas R8A779F0 SoC. + +config CLK_R8A779G0 + bool "Renesas R8A779G0 clock driver" + depends on CLK_RCAR_GEN3 + help + Enable this to support the clocks on Renesas R8A779G0 SoC. |