diff options
| author | Kever Yang <kever.yang@rock-chips.com> | 2017-07-27 07:54:02 +0300 |
|---|---|---|
| committer | Philipp Tomsich <philipp.tomsich@theobroma-systems.com> | 2017-08-13 18:15:09 +0300 |
| commit | 217273cd441fe3d00a1bdad143dcb656854963f9 (patch) | |
| tree | 84b0975bed28db6f6f01bcf59d7d42cd23261e7d /drivers/clk/rockchip/clk_rk3188.c | |
| parent | 3a94d75d0e2a3b2519de51dfa1f369d976d9cccc (diff) | |
| download | u-boot-217273cd441fe3d00a1bdad143dcb656854963f9.tar.xz | |
rockchip: clk: remove RATE_TO_DIV
Use DIV_ROUND_UP instead RATE_TO_DIV for all Rockchip SoC
clock driver.
Add or fix the div-field overflow check at the same time.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Diffstat (limited to 'drivers/clk/rockchip/clk_rk3188.c')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3188.c | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c index cbf31d7de1..8c2c9bc1d8 100644 --- a/drivers/clk/rockchip/clk_rk3188.c +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -71,9 +71,6 @@ enum { SOCSTS_GPLL_LOCK = 1 << 8, }; -#define RATE_TO_DIV(input_rate, output_rate) \ - ((input_rate) / (output_rate) - 1); - #define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) #define PLL_DIVISORS(hz, _nr, _no) {\ @@ -297,7 +294,7 @@ static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, debug("%s: gclk_rate=%u\n", __func__, gclk_rate); /* mmc clock defaulg div 2 internal, need provide double in cru */ - src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq); + src_clk_div = DIV_ROUND_UP(gclk_rate / 2, freq) - 1; assert(src_clk_div <= 0x3f); switch (periph) { @@ -351,8 +348,9 @@ static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate, static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, int periph, uint freq) { - int src_clk_div = RATE_TO_DIV(gclk_rate, freq); + int src_clk_div = DIV_ROUND_UP(gclk_rate, freq) - 1; + assert(src_clk_div < 128); switch (periph) { case SCLK_SPI0: assert(src_clk_div <= SPI0_DIV_MASK); @@ -401,8 +399,8 @@ static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, * reparent aclk_cpu_pre from apll to gpll * set up dependent divisors for PCLK/HCLK and ACLK clocks. */ - aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); - assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + aclk_div = DIV_ROUND_UP(GPLL_HZ, CPU_ACLK_HZ) - 1; + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div <= 0x1f); rk_clrsetreg(&cru->cru_clksel_con[0], CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT | |