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authorQuentin Schulz <quentin.schulz@theobroma-systems.com>2022-11-14 13:33:46 +0300
committerKever Yang <kever.yang@rock-chips.com>2023-01-16 13:01:10 +0300
commit23b71addf90d2df7df591a84ed69300334b26ca9 (patch)
treeeeba4e2a173aa09ab03548885d535f169fa86077 /drivers/clk/rockchip
parent4b564460023a8cbf58d56f354e8ab45264770825 (diff)
downloadu-boot-23b71addf90d2df7df591a84ed69300334b26ca9.tar.xz
rockchip: clk: add watchdog clock to px30_clk_enable
Add the PCLK_WDT_NS clock to px30_clk_enable so that the watchdog driver can probe since it wants to enable this clock. Cc: Quentin Schulz <foss+uboot@0leil.net> Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk_px30.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_px30.c b/drivers/clk/rockchip/clk_px30.c
index 5d467447a1..33a7348b9f 100644
--- a/drivers/clk/rockchip/clk_px30.c
+++ b/drivers/clk/rockchip/clk_px30.c
@@ -1415,6 +1415,9 @@ static int px30_clk_enable(struct clk *clk)
case SCLK_GMAC_RMII:
/* Required to successfully probe the Designware GMAC driver */
return 0;
+ case PCLK_WDT_NS:
+ /* Required to successfully probe the Designware watchdog driver */
+ return 0;
}
debug("%s: unsupported clk %ld\n", __func__, clk->id);