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authorJohan Jonker <jbx6244@gmail.com>2023-03-15 21:34:13 +0300
committerKever Yang <kever.yang@rock-chips.com>2023-04-21 10:16:01 +0300
commit2c2d782556e4f5d9483679d1293d8436892e9fed (patch)
tree99c788612a478013663757bc435b9985f2e5bb54 /drivers/clk/rockchip
parent7c1ee7a8488386e827c274d86297af415e49c02a (diff)
downloadu-boot-2c2d782556e4f5d9483679d1293d8436892e9fed.tar.xz
clk: rockchip: clk_rk3288: add PCLK_RKPWM
The rk3288 pwm nodes synced from Linux make use of PCLK_RKPWM instead of PCLK_PWM. They have the same pclk_cpu parent, so add PCLK_RKPWM to rk3288_clk_get_rate(). Signed-off-by: Johan Jonker <jbx6244@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # chromebook-jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
-rw-r--r--drivers/clk/rockchip/clk_rk3288.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3288.c b/drivers/clk/rockchip/clk_rk3288.c
index 3b29992c3e..ef744c06f3 100644
--- a/drivers/clk/rockchip/clk_rk3288.c
+++ b/drivers/clk/rockchip/clk_rk3288.c
@@ -778,6 +778,7 @@ static ulong rk3288_clk_get_rate(struct clk *clk)
case PCLK_I2C5:
return gclk_rate;
case PCLK_PWM:
+ case PCLK_RKPWM:
return PD_BUS_PCLK_HZ;
case SCLK_SARADC:
new_rate = rockchip_saradc_get_clk(priv->cru);