diff options
| author | Michal Suchanek <msuchanek@suse.de> | 2022-09-28 13:41:29 +0300 |
|---|---|---|
| committer | Sean Anderson <seanga2@gmail.com> | 2022-10-19 19:06:48 +0300 |
| commit | aa36a74f0f2706a27693390c267fe7d6c5600b62 (patch) | |
| tree | cb82dfd9819e6ee403f8a64b8850506d83e75b55 /drivers/clk/rockchip | |
| parent | a1265cd5804474f1c39731c73c65160a1eaf88f4 (diff) | |
| download | u-boot-aa36a74f0f2706a27693390c267fe7d6c5600b62.tar.xz | |
rockchip: clk: pll: Fix constant typo
Fixes: bbda2ed584 ("rockchip: clk: pll: add common pll setting funcs")
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Link: https://lore.kernel.org/r/20220928104129.13240-1-msuchanek@suse.de
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_pll.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/rockchip/clk_pll.c b/drivers/clk/rockchip/clk_pll.c index 8d2aaf5b84..09b97cf57a 100644 --- a/drivers/clk/rockchip/clk_pll.c +++ b/drivers/clk/rockchip/clk_pll.c @@ -31,7 +31,7 @@ static struct rockchip_pll_rate_table rockchip_auto_table; #define RK3036_PLLCON1_DSMPD_SHIFT 12 #define RK3036_PLLCON2_FRAC_MASK 0xffffff #define RK3036_PLLCON2_FRAC_SHIFT 0 -#define RK3036_PLLCON1_PWRDOWN_SHIT 13 +#define RK3036_PLLCON1_PWRDOWN_SHIFT 13 #define MHZ 1000000 #define KHZ 1000 @@ -207,7 +207,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power down */ rk_setreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); rk_clrsetreg(base + pll->con_offset, (RK3036_PLLCON0_POSTDIV1_MASK | @@ -231,7 +231,7 @@ static int rk3036_pll_set_rate(struct rockchip_pll_clock *pll, /* Power Up */ rk_clrreg(base + pll->con_offset + 0x4, - 1 << RK3036_PLLCON1_PWRDOWN_SHIT); + 1 << RK3036_PLLCON1_PWRDOWN_SHIFT); /* waiting for pll lock */ while (!(readl(base + pll->con_offset + 0x4) & (1 << pll->lock_shift))) |