diff options
| author | Vasily Khoruzhick <anarsoul@gmail.com> | 2023-02-24 00:03:32 +0300 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-02-28 13:07:29 +0300 |
| commit | f0eb365e21d93d7d8b34cd84a8db2f26cab6ee9a (patch) | |
| tree | b490ec92a80da9b4ac464f4c3250d98216a85140 /drivers/clk/rockchip | |
| parent | 3a539e0862e5ec996aaf7e2dfd8caa07a457bdd7 (diff) | |
| download | u-boot-f0eb365e21d93d7d8b34cd84a8db2f26cab6ee9a.tar.xz | |
clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.
Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Diffstat (limited to 'drivers/clk/rockchip')
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index d5e45e7602..99c195b3af 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -1442,6 +1442,7 @@ static ulong rk3568_sdmmc_set_clk(struct rk3568_clk_priv *priv, switch (rate) { case OSC_HZ: case 26 * MHz: + case 25 * MHz: src_clk = CLK_SDMMC_SEL_24M; break; case 400 * MHz: @@ -1631,6 +1632,8 @@ static ulong rk3568_emmc_set_clk(struct rk3568_clk_priv *priv, ulong rate) switch (rate) { case OSC_HZ: + case 26 * MHz: + case 25 * MHz: src_clk = CCLK_EMMC_SEL_24M; break; case 52 * MHz: |