diff options
| author | Xingyu Wu <xingyu.wu@starfivetech.com> | 2023-07-07 13:50:11 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-24 08:21:16 +0300 |
| commit | 9adf1cf6096a13c11d2ff57f9132a6ad178d177c (patch) | |
| tree | 04a285d3ca55b12276a7c5092b25e2bd6cb3d265 /drivers/clk/starfive/clk-jh7110-pll.c | |
| parent | 9a12e304dda76e6d06f37e81411677e8ebbb6049 (diff) | |
| download | u-boot-9adf1cf6096a13c11d2ff57f9132a6ad178d177c.tar.xz | |
clk: starfive: jh7110: Add of_xlate ops and macros for clock id conversion
Modify the drivers to add of_xlate ops and transform clock id.
Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Reviewed-by: Torsten Duwe <duwe@suse.de>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Diffstat (limited to 'drivers/clk/starfive/clk-jh7110-pll.c')
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110-pll.c | 29 |
1 files changed, 25 insertions, 4 deletions
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index bb75a6d6cf..1568a1f4cd 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -19,6 +19,8 @@ #include <linux/delay.h> #include <linux/err.h> +#include "clk.h" + #define UBOOT_DM_CLK_JH7110_PLLX "jh7110_clk_pllx" #define PLL_PD_OFF 1 @@ -31,6 +33,8 @@ #define CLK_DDR_BUS_PLL1_DIV4 2 #define CLK_DDR_BUS_PLL1_DIV8 3 +#define JH7110_PLL_ID_TRANS(id) ((id) + JH7110_EXTCLK_END) + enum starfive_pll_type { PLL0 = 0, PLL1, @@ -371,29 +375,46 @@ static int jh7110_pll_clk_probe(struct udevice *dev) if (sysreg == FDT_ADDR_T_NONE) return -EINVAL; - clk_dm(JH7110_SYSCLK_PLL0_OUT, + clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL0_OUT), starfive_jh7110_pll("pll0_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll0)); - clk_dm(JH7110_SYSCLK_PLL1_OUT, + clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL1_OUT), starfive_jh7110_pll("pll1_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll1)); - clk_dm(JH7110_SYSCLK_PLL2_OUT, + clk_dm(JH7110_PLL_ID_TRANS(JH7110_SYSCLK_PLL2_OUT), starfive_jh7110_pll("pll2_out", "oscillator", reg, (void __iomem *)sysreg, &starfive_jh7110_pll2)); return 0; } +static int jh7110_pll_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) +{ + if (args->args_count > 1) { + debug("Invalid args_count: %d\n", args->args_count); + return -EINVAL; + } + + if (args->args_count) + clk->id = JH7110_PLL_ID_TRANS(args->args[0]); + else + clk->id = 0; + + return 0; +} + static const struct udevice_id jh7110_pll_clk_of_match[] = { { .compatible = "starfive,jh7110-pll", }, { } }; +JH7110_CLK_OPS(pll); + /* PLL clk device */ U_BOOT_DRIVER(jh7110_pll_clk) = { .name = "jh7110_pll_clk", .id = UCLASS_CLK, .of_match = jh7110_pll_clk_of_match, .probe = jh7110_pll_clk_probe, - .ops = &ccf_clk_ops, + .ops = &jh7110_pll_clk_ops, }; |