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| author | Samuel Holland <samuel@sholland.org> | 2021-09-11 22:45:31 +0300 |
|---|---|---|
| committer | Andre Przywara <andre.przywara@arm.com> | 2021-10-25 16:54:06 +0300 |
| commit | e0c628d728d6f2b0ab01488706b1a9679512a982 (patch) | |
| tree | 7a86ba4445534ea40155fa42d785e663f7a862c4 /drivers/clk | |
| parent | 0ec88323dae7a91f535c2c9db45cb3c925507ea2 (diff) | |
| download | u-boot-e0c628d728d6f2b0ab01488706b1a9679512a982.tar.xz | |
clk: sunxi: Extend DM_RESET selection to SPL
The sunxi clock driver exposes a reset controller, so it selects the
reset controller framework. Ensure that dependency is also satisfied
when building the driver for the SPL.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/sunxi/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig index f89c7ffd42..f19908113e 100644 --- a/drivers/clk/sunxi/Kconfig +++ b/drivers/clk/sunxi/Kconfig @@ -2,6 +2,7 @@ config CLK_SUNXI bool "Clock support for Allwinner SoCs" depends on CLK && ARCH_SUNXI select DM_RESET + select SPL_DM_RESET if SPL_CLK default y help This enables support for common clock driver API on Allwinner |