diff options
author | Sean Anderson <seanga2@gmail.com> | 2021-04-09 05:13:04 +0300 |
---|---|---|
committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2021-05-14 11:20:47 +0300 |
commit | d0686a02b98ee264532c25108edc3ba44acc1145 (patch) | |
tree | adcffc10cdb141a5aabfc93836602df271c71f7c /drivers/clk | |
parent | 8c12cb3fd80304d4d542d35405aa54ae4a317e9b (diff) | |
download | u-boot-d0686a02b98ee264532c25108edc3ba44acc1145.tar.xz |
clk: k210: Fix PLLs not being enabled
After starting or setting the rate of a PLL, the enable bit must be set.
This fixes a bug where the AI ram would not be accessible, because it
requires PLL1 to be running.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/kendryte/pll.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/drivers/clk/kendryte/pll.c b/drivers/clk/kendryte/pll.c index ab6d75d585..f198920113 100644 --- a/drivers/clk/kendryte/pll.c +++ b/drivers/clk/kendryte/pll.c @@ -531,6 +531,7 @@ static int k210_pll_enable(struct clk *clk) k210_pll_waitfor_lock(pll); reg &= ~K210_PLL_BYPASS; + reg |= K210_PLL_EN; writel(reg, pll->reg); return 0; @@ -550,6 +551,7 @@ static int k210_pll_disable(struct clk *clk) writel(reg, pll->reg); reg &= ~K210_PLL_PWRD; + reg &= ~K210_PLL_EN; writel(reg, pll->reg); return 0; } |