diff options
author | Simon Glass <sjg@chromium.org> | 2020-12-04 02:55:23 +0300 |
---|---|---|
committer | Simon Glass <sjg@chromium.org> | 2020-12-14 02:51:09 +0300 |
commit | 8a8d24bdf174851ebb8607f359d54b72e3283b97 (patch) | |
tree | 89fe2b9fd0c33209ce154170f9bda61f624dd9cd /drivers/clk | |
parent | b012ff1f1b0d662587dcf8707fe7cbf1c1f35d2f (diff) | |
download | u-boot-8a8d24bdf174851ebb8607f359d54b72e3283b97.tar.xz |
dm: treewide: Rename ..._platdata variables to just ..._plat
Try to maintain some consistency between these variables by using _plat as
a suffix for them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/clk')
-rw-r--r-- | drivers/clk/altera/clk-agilex.c | 50 | ||||
-rw-r--r-- | drivers/clk/altera/clk-arria10.c | 18 | ||||
-rw-r--r-- | drivers/clk/at91/compat.c | 50 |
3 files changed, 59 insertions, 59 deletions
diff --git a/drivers/clk/altera/clk-agilex.c b/drivers/clk/altera/clk-agilex.c index e0f43a264c..bac1d98e19 100644 --- a/drivers/clk/altera/clk-agilex.c +++ b/drivers/clk/altera/clk-agilex.c @@ -17,7 +17,7 @@ DECLARE_GLOBAL_DATA_PTR; -struct socfpga_clk_platdata { +struct socfpga_clk_plat { void __iomem *regs; }; @@ -25,20 +25,20 @@ struct socfpga_clk_platdata { * function to write the bypass register which requires a poll of the * busy bit */ -static void clk_write_bypass_mainpll(struct socfpga_clk_platdata *plat, u32 val) +static void clk_write_bypass_mainpll(struct socfpga_clk_plat *plat, u32 val) { CM_REG_WRITEL(plat, val, CLKMGR_MAINPLL_BYPASS); cm_wait_for_fsm(); } -static void clk_write_bypass_perpll(struct socfpga_clk_platdata *plat, u32 val) +static void clk_write_bypass_perpll(struct socfpga_clk_plat *plat, u32 val) { CM_REG_WRITEL(plat, val, CLKMGR_PERPLL_BYPASS); cm_wait_for_fsm(); } /* function to write the ctrl register which requires a poll of the busy bit */ -static void clk_write_ctrl(struct socfpga_clk_platdata *plat, u32 val) +static void clk_write_ctrl(struct socfpga_clk_plat *plat, u32 val) { CM_REG_WRITEL(plat, val, CLKMGR_CTRL); cm_wait_for_fsm(); @@ -108,7 +108,7 @@ static const struct { }, }; -static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll, +static int membus_wait_for_req(struct socfpga_clk_plat *plat, u32 pll, int timeout) { int cnt = 0; @@ -133,7 +133,7 @@ static int membus_wait_for_req(struct socfpga_clk_platdata *plat, u32 pll, return 0; } -static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll, +static int membus_write_pll(struct socfpga_clk_plat *plat, u32 pll, u32 addr_offset, u32 wdat, int timeout) { u32 addr; @@ -154,7 +154,7 @@ static int membus_write_pll(struct socfpga_clk_platdata *plat, u32 pll, return membus_wait_for_req(plat, pll, timeout); } -static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll, +static int membus_read_pll(struct socfpga_clk_plat *plat, u32 pll, u32 addr_offset, u32 *rdata, int timeout) { u32 addr; @@ -184,7 +184,7 @@ static int membus_read_pll(struct socfpga_clk_platdata *plat, u32 pll, return 0; } -static void membus_pll_configs(struct socfpga_clk_platdata *plat, u32 pll) +static void membus_pll_configs(struct socfpga_clk_plat *plat, u32 pll) { int i; u32 rdata; @@ -236,7 +236,7 @@ static u32 calc_vocalib_pll(u32 pllm, u32 pllglob) static void clk_basic_init(struct udevice *dev, const struct cm_config * const cfg) { - struct socfpga_clk_platdata *plat = dev_get_plat(dev); + struct socfpga_clk_plat *plat = dev_get_plat(dev); u32 vcocalib; if (!cfg) @@ -342,7 +342,7 @@ static void clk_basic_init(struct udevice *dev, CM_REG_READL(plat, CLKMGR_CTRL) & ~CLKMGR_CTRL_BOOTMODE); } -static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat, +static u64 clk_get_vco_clk_hz(struct socfpga_clk_plat *plat, u32 pllglob_reg, u32 pllm_reg) { u64 fref, arefdiv, mdiv, reg, vco; @@ -375,26 +375,26 @@ static u64 clk_get_vco_clk_hz(struct socfpga_clk_platdata *plat, return vco; } -static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_platdata *plat) +static u64 clk_get_main_vco_clk_hz(struct socfpga_clk_plat *plat) { return clk_get_vco_clk_hz(plat, CLKMGR_MAINPLL_PLLGLOB, CLKMGR_MAINPLL_PLLM); } -static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_platdata *plat) +static u64 clk_get_per_vco_clk_hz(struct socfpga_clk_plat *plat) { return clk_get_vco_clk_hz(plat, CLKMGR_PERPLL_PLLGLOB, CLKMGR_PERPLL_PLLM); } -static u32 clk_get_5_1_clk_src(struct socfpga_clk_platdata *plat, u64 reg) +static u32 clk_get_5_1_clk_src(struct socfpga_clk_plat *plat, u64 reg) { u32 clksrc = CM_REG_READL(plat, reg); return (clksrc & CLKMGR_CLKSRC_MASK) >> CLKMGR_CLKSRC_OFFSET; } -static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg, +static u64 clk_get_clksrc_hz(struct socfpga_clk_plat *plat, u32 clksrc_reg, u32 main_reg, u32 per_reg) { u64 clock; @@ -431,7 +431,7 @@ static u64 clk_get_clksrc_hz(struct socfpga_clk_platdata *plat, u32 clksrc_reg, return clock; } -static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat) +static u64 clk_get_mpu_clk_hz(struct socfpga_clk_plat *plat) { u64 clock = clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_MPUCLK, CLKMGR_MAINPLL_PLLC0, @@ -443,14 +443,14 @@ static u64 clk_get_mpu_clk_hz(struct socfpga_clk_platdata *plat) return clock; } -static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_platdata *plat) +static u32 clk_get_l3_main_clk_hz(struct socfpga_clk_plat *plat) { return clk_get_clksrc_hz(plat, CLKMGR_MAINPLL_NOCCLK, CLKMGR_MAINPLL_PLLC1, CLKMGR_PERPLL_PLLC1); } -static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat) +static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_plat *plat) { u64 clock = clk_get_l3_main_clk_hz(plat); @@ -461,7 +461,7 @@ static u32 clk_get_l4_main_clk_hz(struct socfpga_clk_platdata *plat) return clock; } -static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat) +static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_plat *plat) { u64 clock = clk_get_clksrc_hz(plat, CLKMGR_ALTR_SDMMCCTR, CLKMGR_MAINPLL_PLLC3, @@ -473,7 +473,7 @@ static u32 clk_get_sdmmc_clk_hz(struct socfpga_clk_platdata *plat) return clock / 4; } -static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat) +static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_plat *plat) { u64 clock = clk_get_l3_main_clk_hz(plat); @@ -484,7 +484,7 @@ static u32 clk_get_l4_sp_clk_hz(struct socfpga_clk_platdata *plat) return clock; } -static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat) +static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_plat *plat) { u64 clock = clk_get_l3_main_clk_hz(plat); @@ -495,7 +495,7 @@ static u32 clk_get_l4_mp_clk_hz(struct socfpga_clk_platdata *plat) return clock; } -static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat) +static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_plat *plat) { if (CM_REG_READL(plat, CLKMGR_STAT) & CLKMGR_STAT_BOOTMODE) return clk_get_l3_main_clk_hz(plat) / 2; @@ -503,7 +503,7 @@ static u32 clk_get_l4_sys_free_clk_hz(struct socfpga_clk_platdata *plat) return clk_get_l3_main_clk_hz(plat) / 4; } -static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id) +static u32 clk_get_emac_clk_hz(struct socfpga_clk_plat *plat, u32 emac_id) { bool emacsel_a; u32 ctl; @@ -585,7 +585,7 @@ static u32 clk_get_emac_clk_hz(struct socfpga_clk_platdata *plat, u32 emac_id) static ulong socfpga_clk_get_rate(struct clk *clk) { - struct socfpga_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_clk_plat *plat = dev_get_plat(clk->dev); switch (clk->id) { case AGILEX_MPU_CLK: @@ -630,7 +630,7 @@ static int socfpga_clk_probe(struct udevice *dev) static int socfpga_clk_of_to_plat(struct udevice *dev) { - struct socfpga_clk_platdata *plat = dev_get_plat(dev); + struct socfpga_clk_plat *plat = dev_get_plat(dev); fdt_addr_t addr; addr = dev_read_addr(dev); @@ -658,5 +658,5 @@ U_BOOT_DRIVER(socfpga_agilex_clk) = { .ops = &socfpga_clk_ops, .probe = socfpga_clk_probe, .of_to_plat = socfpga_clk_of_to_plat, - .plat_auto = sizeof(struct socfpga_clk_platdata), + .plat_auto = sizeof(struct socfpga_clk_plat), }; diff --git a/drivers/clk/altera/clk-arria10.c b/drivers/clk/altera/clk-arria10.c index e1e4876025..1812152d56 100644 --- a/drivers/clk/altera/clk-arria10.c +++ b/drivers/clk/altera/clk-arria10.c @@ -24,7 +24,7 @@ enum socfpga_a10_clk_type { SOCFPGA_A10_CLK_UNKNOWN_CLK, }; -struct socfpga_a10_clk_platdata { +struct socfpga_a10_clk_plat { enum socfpga_a10_clk_type type; struct clk_bulk clks; u32 regs; @@ -43,7 +43,7 @@ struct socfpga_a10_clk_platdata { static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev); u32 reg, maxval; if (plat->clks.count == 0) @@ -84,7 +84,7 @@ static int socfpga_a10_clk_get_upstream(struct clk *clk, struct clk **upclk) static int socfpga_a10_clk_endisable(struct clk *clk, bool enable) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev); struct clk *upclk = NULL; int ret; @@ -120,7 +120,7 @@ static int socfpga_a10_clk_disable(struct clk *clk) static ulong socfpga_a10_clk_get_rate(struct clk *clk) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(clk->dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(clk->dev); struct clk *upclk = NULL; ulong rate = 0, reg, numer, denom; int ret; @@ -190,7 +190,7 @@ static struct clk_ops socfpga_a10_clk_ops = { */ static void socfpga_a10_handoff_workaround(struct udevice *dev) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(dev); const void *fdt = gd->fdt_blob; struct clk_bulk *bulk = &plat->clks; int i, ret, offset = dev_of_offset(dev); @@ -274,8 +274,8 @@ static int socfpga_a10_clk_bind(struct udevice *dev) static int socfpga_a10_clk_probe(struct udevice *dev) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); - struct socfpga_a10_clk_platdata *pplat; + struct socfpga_a10_clk_plat *plat = dev_get_plat(dev); + struct socfpga_a10_clk_plat *pplat; struct udevice *pdev; const void *fdt = gd->fdt_blob; int offset = dev_of_offset(dev); @@ -321,7 +321,7 @@ static int socfpga_a10_clk_probe(struct udevice *dev) static int socfpga_a10_of_to_plat(struct udevice *dev) { - struct socfpga_a10_clk_platdata *plat = dev_get_plat(dev); + struct socfpga_a10_clk_plat *plat = dev_get_plat(dev); unsigned int divreg[3], gatereg[2]; int ret; @@ -359,5 +359,5 @@ U_BOOT_DRIVER(socfpga_a10_clk) = { .probe = socfpga_a10_clk_probe, .of_to_plat = socfpga_a10_of_to_plat, - .plat_auto = sizeof(struct socfpga_a10_clk_platdata), + .plat_auto = sizeof(struct socfpga_a10_clk_plat), }; diff --git a/drivers/clk/at91/compat.c b/drivers/clk/at91/compat.c index 89283e6e36..e514f26656 100644 --- a/drivers/clk/at91/compat.c +++ b/drivers/clk/at91/compat.c @@ -21,7 +21,7 @@ DECLARE_GLOBAL_DATA_PTR; -struct pmc_platdata { +struct pmc_plat { struct at91_pmc *reg_base; struct regmap *regmap_sfr; }; @@ -45,7 +45,7 @@ U_BOOT_DRIVER(at91_pmc) = { static int at91_pmc_core_probe(struct udevice *dev) { - struct pmc_platdata *plat = dev_get_plat(dev); + struct pmc_plat *plat = dev_get_plat(dev); dev = dev_get_parent(dev); @@ -115,7 +115,7 @@ int at91_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args) int at91_clk_probe(struct udevice *dev) { struct udevice *dev_periph_container, *dev_pmc; - struct pmc_platdata *plat = dev_get_plat(dev); + struct pmc_plat *plat = dev_get_plat(dev); dev_periph_container = dev_get_parent(dev); dev_pmc = dev_get_parent(dev_periph_container); @@ -191,7 +191,7 @@ U_BOOT_DRIVER(at91_master_clk) = { /* Main osc clock specific code. */ static int main_osc_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; if (readl(&pmc->sr) & AT91_PMC_MOSCSELS) @@ -225,14 +225,14 @@ U_BOOT_DRIVER(at91sam9x5_main_osc_clk) = { .id = UCLASS_CLK, .of_match = main_osc_clk_match, .probe = main_osc_clk_probe, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &main_osc_clk_ops, }; /* PLLA clock specific code. */ static int plla_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; if (readl(&pmc->sr) & AT91_PMC_LOCKA) @@ -266,7 +266,7 @@ U_BOOT_DRIVER(at91_plla_clk) = { .id = UCLASS_CLK, .of_match = plla_clk_match, .probe = plla_clk_probe, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &plla_clk_ops, }; @@ -278,7 +278,7 @@ static int at91_plladiv_clk_enable(struct clk *clk) static ulong at91_plladiv_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk source; ulong clk_rate; @@ -297,7 +297,7 @@ static ulong at91_plladiv_clk_get_rate(struct clk *clk) static ulong at91_plladiv_clk_set_rate(struct clk *clk, ulong rate) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk source; ulong parent_rate; @@ -340,7 +340,7 @@ U_BOOT_DRIVER(at91_plladiv_clk) = { .id = UCLASS_CLK, .of_match = at91_plladiv_clk_match, .probe = at91_plladiv_clk_probe, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &at91_plladiv_clk_ops, }; @@ -401,7 +401,7 @@ static ulong system_clk_set_rate(struct clk *clk, ulong rate) static int system_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; u32 mask; @@ -437,7 +437,7 @@ U_BOOT_DRIVER(system_clk) = { .name = "system-clk", .id = UCLASS_CLK, .probe = at91_clk_probe, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &system_clk_ops, }; @@ -483,7 +483,7 @@ U_BOOT_DRIVER(sam9x5_periph_clk) = { static int periph_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; enum periph_clk_type clk_type; void *addr; @@ -536,7 +536,7 @@ static struct clk_ops periph_clk_ops = { U_BOOT_DRIVER(clk_periph) = { .name = "periph-clk", .id = UCLASS_CLK, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .probe = at91_clk_probe, .ops = &periph_clk_ops, }; @@ -552,7 +552,7 @@ U_BOOT_DRIVER(clk_periph) = { static int utmi_clk_enable(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk clk_dev; ulong clk_rate; @@ -640,7 +640,7 @@ static struct clk_ops utmi_clk_ops = { static int utmi_clk_of_to_plat(struct udevice *dev) { - struct pmc_platdata *plat = dev_get_plat(dev); + struct pmc_plat *plat = dev_get_plat(dev); struct udevice *syscon; uclass_get_device_by_phandle(UCLASS_SYSCON, dev, @@ -668,7 +668,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { .of_match = utmi_clk_match, .probe = utmi_clk_probe, .of_to_plat = utmi_clk_of_to_plat, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &utmi_clk_ops, }; @@ -681,7 +681,7 @@ U_BOOT_DRIVER(at91sam9x5_utmi_clk) = { static ulong sama5d4_h32mx_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; ulong rate = gd->arch.mck_rate_hz; @@ -713,7 +713,7 @@ U_BOOT_DRIVER(sama5d4_h32mx_clk) = { .id = UCLASS_CLK, .of_match = sama5d4_h32mx_clk_match, .probe = sama5d4_h32mx_clk_probe, - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &sama5d4_h32mx_clk_ops, }; @@ -754,7 +754,7 @@ struct generic_clk_priv { static ulong generic_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk parent; ulong clk_rate; @@ -782,7 +782,7 @@ static ulong generic_clk_get_rate(struct clk *clk) static ulong generic_clk_set_rate(struct clk *clk, ulong rate) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct generic_clk_priv *priv = dev_get_priv(clk->dev); struct clk parent, best_parent; @@ -877,7 +877,7 @@ U_BOOT_DRIVER(generic_clk) = { .probe = at91_clk_probe, .of_to_plat = generic_clk_of_to_plat, .priv_auto = sizeof(struct generic_clk_priv), - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &generic_clk_ops, }; @@ -895,7 +895,7 @@ struct at91_usb_clk_priv { static ulong at91_usb_clk_get_rate(struct clk *clk) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct clk source; u32 tmp, usbdiv; @@ -916,7 +916,7 @@ static ulong at91_usb_clk_get_rate(struct clk *clk) static ulong at91_usb_clk_set_rate(struct clk *clk, ulong rate) { - struct pmc_platdata *plat = dev_get_plat(clk->dev); + struct pmc_plat *plat = dev_get_plat(clk->dev); struct at91_pmc *pmc = plat->reg_base; struct at91_usb_clk_priv *priv = dev_get_priv(clk->dev); struct clk source, best_source; @@ -1013,7 +1013,7 @@ U_BOOT_DRIVER(at91_usb_clk) = { .probe = at91_usb_clk_probe, .of_to_plat = at91_usb_clk_of_to_plat, .priv_auto = sizeof(struct at91_usb_clk_priv), - .plat_auto = sizeof(struct pmc_platdata), + .plat_auto = sizeof(struct pmc_plat), .ops = &at91_usb_clk_ops, }; |