diff options
| author | Hoegeun Kwon <hoegeun.kwon@samsung.com> | 2023-06-28 13:19:49 +0300 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-07-06 12:28:08 +0300 |
| commit | 422fc299df9b873e7e485db08621e5fb499c6a8f (patch) | |
| tree | fa9d6eaa2c14c616281768c49b56249d881a0204 /drivers/clk | |
| parent | 0a8239afa3c1439bbaa7dd1ad0c23efabf93140b (diff) | |
| download | u-boot-422fc299df9b873e7e485db08621e5fb499c6a8f.tar.xz | |
clk: starfive: pll: Fix to use postdiv1_mask
There is a problem that the rates of PLL0 and PLL1 are set incorrectly
because the postdiv1_mask value is incorrectly entered when setting
the pll clk reg. Modify postdiv1's mask value to be put correctly.
Signed-off-by: Hoegeun Kwon <hoegeun.kwon@samsung.com>
Reviewed-by: Minkyu Kang <mk7.kang@samsung.com>
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/starfive/clk-jh7110-pll.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/starfive/clk-jh7110-pll.c b/drivers/clk/starfive/clk-jh7110-pll.c index 02e6d9000e..7492b1f70d 100644 --- a/drivers/clk/starfive/clk-jh7110-pll.c +++ b/drivers/clk/starfive/clk-jh7110-pll.c @@ -185,7 +185,7 @@ static void jh7110_pll_set_rate(struct clk_jh7110_pllx *pll, PLLX_SET(pll->offset->dsmpd, pll->offset->dsmpd_mask, 1); PLLX_SET(pll->offset->prediv, pll->offset->prediv_mask, rate->prediv); PLLX_SET(pll->offset->fbdiv, pll->offset->fbdiv_mask, rate->fbdiv); - PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1, 0); + PLLX_SET(pll->offset->postdiv1, pll->offset->postdiv1_mask, 0); PLLX_SET(pll->offset->pd, pll->offset->pd_mask, PLL_PD_ON); if (set) { |