Merge https://source.denx.de/u-boot/custodians/u-boot-sunxi

The bulk of it is Samuel's DM_I2C rework, which removes the nasty I2C
deprecation warnings for most 32-bit boards. It also includes some
smaller refactorings that pave the way for more changes, mostly driven
by needing to support the Allwinner RISC-V SoC later on.

Board wise we gain support for the FriendlyARM NanoPi R1S H5 router
board and official Pinetab support.

Build-tested for all 160 sunxi boards, and boot tested on a A64, A20,
H3, H6, and H616 board. USB, SD card, eMMC, and Ethernet all work there
(where applicable).

17 files changed, 235 insertions, 13 deletions

diff --git a/drivers/clk/sunxi/Kconfig b/drivers/clk/sunxi/Kconfig
index bf084fa7a8..f89c7ffd42 100644
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -30,6 +30,13 @@ config CLK_SUN6I_A31
 	  This enables common clock driver support for platforms based
 	  on Allwinner A31/A31s SoC.
 
+config CLK_SUN6I_A31_R
+	bool "Clock driver for Allwinner A31 generation PRCM"
+	default SUNXI_GEN_SUN6I
+	help
+	  This enables common clock driver support for the PRCM
+	  in Allwinner A31/A31s/A23/A33/A83T/H3/A64/H5 SoCs.
+
 config CLK_SUN8I_A23
 	bool "Clock driver for Allwinner A23/A33"
 	default MACH_SUN8I_A23 || MACH_SUN8I_A33
@@ -79,6 +86,13 @@ config CLK_SUN50I_H6
 	  This enables common clock driver support for platforms based
 	  on Allwinner H6 SoC.
 
+config CLK_SUN50I_H6_R
+	bool "Clock driver for Allwinner H6 generation PRCM"
+	default SUN50I_GEN_H6
+	help
+	  This enables common clock driver support for the PRCM
+	  in Allwinner H6/H616 SoCs.
+
 config CLK_SUN50I_H616
 	bool "Clock driver for Allwinner H616"
 	default MACH_SUN50I_H616
diff --git a/drivers/clk/sunxi/Makefile b/drivers/clk/sunxi/Makefile
index 4f9282a8b9..48a48a2f00 100644
--- a/drivers/clk/sunxi/Makefile
+++ b/drivers/clk/sunxi/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_CLK_SUNXI) += clk_sun6i_rtc.o
 obj-$(CONFIG_CLK_SUN4I_A10) += clk_a10.o
 obj-$(CONFIG_CLK_SUN5I_A10S) += clk_a10s.o
 obj-$(CONFIG_CLK_SUN6I_A31) += clk_a31.o
+obj-$(CONFIG_CLK_SUN6I_A31_R) += clk_a31_r.o
 obj-$(CONFIG_CLK_SUN8I_A23) += clk_a23.o
 obj-$(CONFIG_CLK_SUN8I_A83T) += clk_a83t.o
 obj-$(CONFIG_CLK_SUN8I_R40) += clk_r40.o
@@ -18,5 +19,6 @@ obj-$(CONFIG_CLK_SUN8I_V3S) += clk_v3s.o
 obj-$(CONFIG_CLK_SUN9I_A80) += clk_a80.o
 obj-$(CONFIG_CLK_SUN8I_H3) += clk_h3.o
 obj-$(CONFIG_CLK_SUN50I_H6) += clk_h6.o
+obj-$(CONFIG_CLK_SUN50I_H6_R) += clk_h6_r.o
 obj-$(CONFIG_CLK_SUN50I_H616) += clk_h616.o
 obj-$(CONFIG_CLK_SUN50I_A64) += clk_a64.o
diff --git a/drivers/clk/sunxi/clk_a10.c b/drivers/clk/sunxi/clk_a10.c
index 1b5de86e20..90b929d3d3 100644
--- a/drivers/clk/sunxi/clk_a10.c
+++ b/drivers/clk/sunxi/clk_a10.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun4i-a10-ccu.h>
 #include <dt-bindings/reset/sun4i-a10-ccu.h>
 #include <linux/bitops.h>
@@ -31,6 +31,11 @@ static struct ccu_clk_gate a10_gates[] = {
 
 	[CLK_AHB_GMAC]		= GATE(0x064, BIT(17)),
 
+	[CLK_APB1_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_APB1_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_APB1_I2C2]		= GATE(0x06c, BIT(2)),
+	[CLK_APB1_I2C3]		= GATE(0x06c, BIT(3)),
+	[CLK_APB1_I2C4]		= GATE(0x06c, BIT(15)),
 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
 	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a10s.c b/drivers/clk/sunxi/clk_a10s.c
index 184f61ab23..addf4f4d5c 100644
--- a/drivers/clk/sunxi/clk_a10s.c
+++ b/drivers/clk/sunxi/clk_a10s.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun5i-ccu.h>
 #include <dt-bindings/reset/sun5i-ccu.h>
 #include <linux/bitops.h>
@@ -25,6 +25,9 @@ static struct ccu_clk_gate a10s_gates[] = {
 	[CLK_AHB_SPI1]		= GATE(0x060, BIT(21)),
 	[CLK_AHB_SPI2]		= GATE(0x060, BIT(22)),
 
+	[CLK_APB1_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_APB1_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_APB1_I2C2]		= GATE(0x06c, BIT(2)),
 	[CLK_APB1_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB1_UART1]	= GATE(0x06c, BIT(17)),
 	[CLK_APB1_UART2]	= GATE(0x06c, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a23.c b/drivers/clk/sunxi/clk_a23.c
index 5750514a74..c45d2c3529 100644
--- a/drivers/clk/sunxi/clk_a23.c
+++ b/drivers/clk/sunxi/clk_a23.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun8i-a23-a33-ccu.h>
 #include <dt-bindings/reset/sun8i-a23-a33-ccu.h>
 #include <linux/bitops.h>
@@ -23,6 +23,9 @@ static struct ccu_clk_gate a23_gates[] = {
 	[CLK_BUS_EHCI]		= GATE(0x060, BIT(26)),
 	[CLK_BUS_OHCI]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
@@ -53,6 +56,9 @@ static struct ccu_reset a23_resets[] = {
 	[RST_BUS_EHCI]		= RESET(0x2c0, BIT(26)),
 	[RST_BUS_OHCI]		= RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
+	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a31.c b/drivers/clk/sunxi/clk_a31.c
index 9226112f4a..251fc3b705 100644
--- a/drivers/clk/sunxi/clk_a31.c
+++ b/drivers/clk/sunxi/clk_a31.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun6i-a31-ccu.h>
 #include <dt-bindings/reset/sun6i-a31-ccu.h>
 #include <linux/bitops.h>
@@ -30,6 +30,10 @@ static struct ccu_clk_gate a31_gates[] = {
 	[CLK_AHB1_OHCI1]	= GATE(0x060, BIT(30)),
 	[CLK_AHB1_OHCI2]	= GATE(0x060, BIT(31)),
 
+	[CLK_APB2_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_APB2_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_APB2_I2C2]		= GATE(0x06c, BIT(2)),
+	[CLK_APB2_I2C3]		= GATE(0x06c, BIT(3)),
 	[CLK_APB2_UART0]	= GATE(0x06c, BIT(16)),
 	[CLK_APB2_UART1]	= GATE(0x06c, BIT(17)),
 	[CLK_APB2_UART2]	= GATE(0x06c, BIT(18)),
@@ -71,6 +75,10 @@ static struct ccu_reset a31_resets[] = {
 	[RST_AHB1_OHCI1]	= RESET(0x2c0, BIT(30)),
 	[RST_AHB1_OHCI2]	= RESET(0x2c0, BIT(31)),
 
+	[RST_APB2_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_APB2_I2C1]		= RESET(0x2d8, BIT(1)),
+	[RST_APB2_I2C2]		= RESET(0x2d8, BIT(2)),
+	[RST_APB2_I2C3]		= RESET(0x2d8, BIT(3)),
 	[RST_APB2_UART0]	= RESET(0x2d8, BIT(16)),
 	[RST_APB2_UART1]	= RESET(0x2d8, BIT(17)),
 	[RST_APB2_UART2]	= RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a31_r.c b/drivers/clk/sunxi/clk_a31_r.c
new file mode 100644
index 0000000000..1f08ea956f
--- /dev/null
+++ b/drivers/clk/sunxi/clk_a31_r.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun8i-r-ccu.h>
+#include <dt-bindings/reset/sun8i-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate a31_r_gates[] = {
+	[CLK_APB0_PIO]		= GATE(0x028, BIT(0)),
+	[CLK_APB0_IR]		= GATE(0x028, BIT(1)),
+	[CLK_APB0_TIMER]	= GATE(0x028, BIT(2)),
+	[CLK_APB0_RSB]		= GATE(0x028, BIT(3)),
+	[CLK_APB0_UART]		= GATE(0x028, BIT(4)),
+	[CLK_APB0_I2C]		= GATE(0x028, BIT(6)),
+	[CLK_APB0_TWD]		= GATE(0x028, BIT(7)),
+};
+
+static struct ccu_reset a31_r_resets[] = {
+	[RST_APB0_IR]		= RESET(0x0b0, BIT(1)),
+	[RST_APB0_TIMER]	= RESET(0x0b0, BIT(2)),
+	[RST_APB0_RSB]		= RESET(0x0b0, BIT(3)),
+	[RST_APB0_UART]		= RESET(0x0b0, BIT(4)),
+	[RST_APB0_I2C]		= RESET(0x0b0, BIT(6)),
+};
+
+static const struct ccu_desc a31_r_ccu_desc = {
+	.gates = a31_r_gates,
+	.resets = a31_r_resets,
+};
+
+static int a31_r_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(a31_r_resets));
+}
+
+static const struct udevice_id a31_r_clk_ids[] = {
+	{ .compatible = "allwinner,sun8i-a83t-r-ccu",
+	  .data = (ulong)&a31_r_ccu_desc },
+	{ .compatible = "allwinner,sun8i-h3-r-ccu",
+	  .data = (ulong)&a31_r_ccu_desc },
+	{ .compatible = "allwinner,sun50i-a64-r-ccu",
+	  .data = (ulong)&a31_r_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun6i_a31_r) = {
+	.name		= "sun6i_a31_r_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= a31_r_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= a31_r_clk_bind,
+};
diff --git a/drivers/clk/sunxi/clk_a64.c b/drivers/clk/sunxi/clk_a64.c
index 0553ffa439..1004a79503 100644
--- a/drivers/clk/sunxi/clk_a64.c
+++ b/drivers/clk/sunxi/clk_a64.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun50i-a64-ccu.h>
 #include <dt-bindings/reset/sun50i-a64-ccu.h>
 #include <linux/bitops.h>
@@ -26,6 +26,9 @@ static const struct ccu_clk_gate a64_gates[] = {
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(28)),
 	[CLK_BUS_OHCI1]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
@@ -60,6 +63,9 @@ static const struct ccu_reset a64_resets[] = {
 	[RST_BUS_OHCI0]         = RESET(0x2c0, BIT(28)),
 	[RST_BUS_OHCI1]         = RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
+	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a80.c b/drivers/clk/sunxi/clk_a80.c
index 68973d528e..8a0834d83a 100644
--- a/drivers/clk/sunxi/clk_a80.c
+++ b/drivers/clk/sunxi/clk_a80.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun9i-a80-ccu.h>
 #include <dt-bindings/reset/sun9i-a80-ccu.h>
 #include <linux/bitops.h>
@@ -25,6 +25,11 @@ static const struct ccu_clk_gate a80_gates[] = {
 	[CLK_BUS_SPI2]		= GATE(0x580, BIT(22)),
 	[CLK_BUS_SPI3]		= GATE(0x580, BIT(23)),
 
+	[CLK_BUS_I2C0]		= GATE(0x594, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x594, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x594, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x594, BIT(3)),
+	[CLK_BUS_I2C4]		= GATE(0x594, BIT(4)),
 	[CLK_BUS_UART0]		= GATE(0x594, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x594, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x594, BIT(18)),
@@ -40,6 +45,11 @@ static const struct ccu_reset a80_resets[] = {
 	[RST_BUS_SPI2]		= RESET(0x5a0, BIT(22)),
 	[RST_BUS_SPI3]		= RESET(0x5a0, BIT(23)),
 
+	[RST_BUS_I2C0]		= RESET(0x5b4, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x5b4, BIT(1)),
+	[RST_BUS_I2C2]		= RESET(0x5b4, BIT(2)),
+	[RST_BUS_I2C3]		= RESET(0x5b4, BIT(3)),
+	[RST_BUS_I2C4]		= RESET(0x5b4, BIT(4)),
 	[RST_BUS_UART0]		= RESET(0x5b4, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x5b4, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x5b4, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_a83t.c b/drivers/clk/sunxi/clk_a83t.c
index 880c7d7599..8c6043f51e 100644
--- a/drivers/clk/sunxi/clk_a83t.c
+++ b/drivers/clk/sunxi/clk_a83t.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun8i-a83t-ccu.h>
 #include <dt-bindings/reset/sun8i-a83t-ccu.h>
 #include <linux/bitops.h>
@@ -25,6 +25,9 @@ static struct ccu_clk_gate a83t_gates[] = {
 	[CLK_BUS_EHCI1]		= GATE(0x060, BIT(27)),
 	[CLK_BUS_OHCI0]		= GATE(0x060, BIT(29)),
 
+	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
@@ -57,6 +60,9 @@ static struct ccu_reset a83t_resets[] = {
 	[RST_BUS_EHCI1]		= RESET(0x2c0, BIT(27)),
 	[RST_BUS_OHCI0]		= RESET(0x2c0, BIT(29)),
 
+	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
+	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h3.c b/drivers/clk/sunxi/clk_h3.c
index f81633b92d..59afba53ee 100644
--- a/drivers/clk/sunxi/clk_h3.c
+++ b/drivers/clk/sunxi/clk_h3.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun8i-h3-ccu.h>
 #include <dt-bindings/reset/sun8i-h3-ccu.h>
 #include <linux/bitops.h>
@@ -30,6 +30,9 @@ static struct ccu_clk_gate h3_gates[] = {
 	[CLK_BUS_OHCI2]		= GATE(0x060, BIT(30)),
 	[CLK_BUS_OHCI3]		= GATE(0x060, BIT(31)),
 
+	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
@@ -74,6 +77,9 @@ static struct ccu_reset h3_resets[] = {
 
 	[RST_BUS_EPHY]		= RESET(0x2c8, BIT(2)),
 
+	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
+	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_h6.c b/drivers/clk/sunxi/clk_h6.c
index df93d96b3b..4a53788352 100644
--- a/drivers/clk/sunxi/clk_h6.c
+++ b/drivers/clk/sunxi/clk_h6.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun50i-h6-ccu.h>
 #include <dt-bindings/reset/sun50i-h6-ccu.h>
 #include <linux/bitops.h>
@@ -22,6 +22,11 @@ static struct ccu_clk_gate h6_gates[] = {
 	[CLK_BUS_UART2]		= GATE(0x90c, BIT(2)),
 	[CLK_BUS_UART3]		= GATE(0x90c, BIT(3)),
 
+	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
+
 	[CLK_SPI0]		= GATE(0x940, BIT(31)),
 	[CLK_SPI1]		= GATE(0x944, BIT(31)),
 
@@ -57,6 +62,11 @@ static struct ccu_reset h6_resets[] = {
 	[RST_BUS_UART2]		= RESET(0x90c, BIT(18)),
 	[RST_BUS_UART3]		= RESET(0x90c, BIT(19)),
 
+	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
+	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
+	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
+	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
+
 	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
 	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
 
diff --git a/drivers/clk/sunxi/clk_h616.c b/drivers/clk/sunxi/clk_h616.c
index 553d7c6e55..af97d3bb9f 100644
--- a/drivers/clk/sunxi/clk_h616.c
+++ b/drivers/clk/sunxi/clk_h616.c
@@ -7,7 +7,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun50i-h616-ccu.h>
 #include <dt-bindings/reset/sun50i-h616-ccu.h>
 #include <linux/bitops.h>
@@ -24,6 +24,12 @@ static struct ccu_clk_gate h616_gates[] = {
 	[CLK_BUS_UART4]		= GATE(0x90c, BIT(4)),
 	[CLK_BUS_UART5]		= GATE(0x90c, BIT(5)),
 
+	[CLK_BUS_I2C0]		= GATE(0x91c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x91c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x91c, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x91c, BIT(3)),
+	[CLK_BUS_I2C4]		= GATE(0x91c, BIT(4)),
+
 	[CLK_SPI0]		= GATE(0x940, BIT(31)),
 	[CLK_SPI1]		= GATE(0x944, BIT(31)),
 
@@ -68,6 +74,12 @@ static struct ccu_reset h616_resets[] = {
 	[RST_BUS_UART4]		= RESET(0x90c, BIT(20)),
 	[RST_BUS_UART5]		= RESET(0x90c, BIT(21)),
 
+	[RST_BUS_I2C0]		= RESET(0x91c, BIT(16)),
+	[RST_BUS_I2C1]		= RESET(0x91c, BIT(17)),
+	[RST_BUS_I2C2]		= RESET(0x91c, BIT(18)),
+	[RST_BUS_I2C3]		= RESET(0x91c, BIT(19)),
+	[RST_BUS_I2C4]		= RESET(0x91c, BIT(20)),
+
 	[RST_BUS_SPI0]		= RESET(0x96c, BIT(16)),
 	[RST_BUS_SPI1]		= RESET(0x96c, BIT(17)),
 
diff --git a/drivers/clk/sunxi/clk_h6_r.c b/drivers/clk/sunxi/clk_h6_r.c
new file mode 100644
index 0000000000..b9e527e16a
--- /dev/null
+++ b/drivers/clk/sunxi/clk_h6_r.c
@@ -0,0 +1,61 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (C) Samuel Holland <samuel@sholland.org>
+ */
+
+#include <clk-uclass.h>
+#include <dm.h>
+#include <clk/sunxi.h>
+#include <dt-bindings/clock/sun50i-h6-r-ccu.h>
+#include <dt-bindings/reset/sun50i-h6-r-ccu.h>
+#include <linux/bitops.h>
+
+static struct ccu_clk_gate h6_r_gates[] = {
+	[CLK_R_APB1_TIMER]	= GATE(0x11c, BIT(0)),
+	[CLK_R_APB1_TWD]	= GATE(0x12c, BIT(0)),
+	[CLK_R_APB1_PWM]	= GATE(0x13c, BIT(0)),
+	[CLK_R_APB2_UART]	= GATE(0x18c, BIT(0)),
+	[CLK_R_APB2_I2C]	= GATE(0x19c, BIT(0)),
+	[CLK_R_APB2_RSB]	= GATE(0x1bc, BIT(0)),
+	[CLK_R_APB1_IR]		= GATE(0x1cc, BIT(0)),
+	[CLK_R_APB1_W1]		= GATE(0x1ec, BIT(0)),
+};
+
+static struct ccu_reset h6_r_resets[] = {
+	[RST_R_APB1_TIMER]	= RESET(0x11c, BIT(16)),
+	[RST_R_APB1_TWD]	= RESET(0x12c, BIT(16)),
+	[RST_R_APB1_PWM]	= RESET(0x13c, BIT(16)),
+	[RST_R_APB2_UART]	= RESET(0x18c, BIT(16)),
+	[RST_R_APB2_I2C]	= RESET(0x19c, BIT(16)),
+	[RST_R_APB2_RSB]	= RESET(0x1bc, BIT(16)),
+	[RST_R_APB1_IR]		= RESET(0x1cc, BIT(16)),
+	[RST_R_APB1_W1]		= RESET(0x1ec, BIT(16)),
+};
+
+static const struct ccu_desc h6_r_ccu_desc = {
+	.gates = h6_r_gates,
+	.resets = h6_r_resets,
+};
+
+static int h6_r_clk_bind(struct udevice *dev)
+{
+	return sunxi_reset_bind(dev, ARRAY_SIZE(h6_r_resets));
+}
+
+static const struct udevice_id h6_r_clk_ids[] = {
+	{ .compatible = "allwinner,sun50i-h6-r-ccu",
+	  .data = (ulong)&h6_r_ccu_desc },
+	{ .compatible = "allwinner,sun50i-h616-r-ccu",
+	  .data = (ulong)&h6_r_ccu_desc },
+	{ }
+};
+
+U_BOOT_DRIVER(clk_sun6i_h6_r) = {
+	.name		= "sun6i_h6_r_ccu",
+	.id		= UCLASS_CLK,
+	.of_match	= h6_r_clk_ids,
+	.priv_auto	= sizeof(struct ccu_priv),
+	.ops		= &sunxi_clk_ops,
+	.probe		= sunxi_clk_probe,
+	.bind		= h6_r_clk_bind,
+};
diff --git a/drivers/clk/sunxi/clk_r40.c b/drivers/clk/sunxi/clk_r40.c
index ee1e86d22e..4d5b69a976 100644
--- a/drivers/clk/sunxi/clk_r40.c
+++ b/drivers/clk/sunxi/clk_r40.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun8i-r40-ccu.h>
 #include <dt-bindings/reset/sun8i-r40-ccu.h>
 #include <linux/bitops.h>
@@ -32,6 +32,11 @@ static struct ccu_clk_gate r40_gates[] = {
 
 	[CLK_BUS_GMAC]		= GATE(0x064, BIT(17)),
 
+	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
+	[CLK_BUS_I2C2]		= GATE(0x06c, BIT(2)),
+	[CLK_BUS_I2C3]		= GATE(0x06c, BIT(3)),
+	[CLK_BUS_I2C4]		= GATE(0x06c, BIT(15)),
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
@@ -77,6 +82,11 @@ static struct ccu_reset r40_resets[] = {
 
 	[RST_BUS_GMAC]		= RESET(0x2c4, BIT(17)),
 
+	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
+	[RST_BUS_I2C2]		= RESET(0x2d8, BIT(2)),
+	[RST_BUS_I2C3]		= RESET(0x2d8, BIT(3)),
+	[RST_BUS_I2C4]		= RESET(0x2d8, BIT(15)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),
diff --git a/drivers/clk/sunxi/clk_sunxi.c b/drivers/clk/sunxi/clk_sunxi.c
index 41934cd826..9673b58a49 100644
--- a/drivers/clk/sunxi/clk_sunxi.c
+++ b/drivers/clk/sunxi/clk_sunxi.c
@@ -11,7 +11,7 @@
 #include <log.h>
 #include <reset.h>
 #include <asm/io.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <linux/bitops.h>
 #include <linux/log2.h>
 
diff --git a/drivers/clk/sunxi/clk_v3s.c b/drivers/clk/sunxi/clk_v3s.c
index 29622199fd..cce5c658ca 100644
--- a/drivers/clk/sunxi/clk_v3s.c
+++ b/drivers/clk/sunxi/clk_v3s.c
@@ -8,7 +8,7 @@
 #include <clk-uclass.h>
 #include <dm.h>
 #include <errno.h>
-#include <asm/arch/ccu.h>
+#include <clk/sunxi.h>
 #include <dt-bindings/clock/sun8i-v3s-ccu.h>
 #include <dt-bindings/reset/sun8i-v3s-ccu.h>
 #include <linux/bitops.h>
@@ -20,6 +20,8 @@ static struct ccu_clk_gate v3s_gates[] = {
 	[CLK_BUS_SPI0]		= GATE(0x060, BIT(20)),
 	[CLK_BUS_OTG]		= GATE(0x060, BIT(24)),
 
+	[CLK_BUS_I2C0]		= GATE(0x06c, BIT(0)),
+	[CLK_BUS_I2C1]		= GATE(0x06c, BIT(1)),
 	[CLK_BUS_UART0]		= GATE(0x06c, BIT(16)),
 	[CLK_BUS_UART1]		= GATE(0x06c, BIT(17)),
 	[CLK_BUS_UART2]		= GATE(0x06c, BIT(18)),
@@ -38,6 +40,8 @@ static struct ccu_reset v3s_resets[] = {
 	[RST_BUS_SPI0]		= RESET(0x2c0, BIT(20)),
 	[RST_BUS_OTG]		= RESET(0x2c0, BIT(24)),
 
+	[RST_BUS_I2C0]		= RESET(0x2d8, BIT(0)),
+	[RST_BUS_I2C1]		= RESET(0x2d8, BIT(1)),
 	[RST_BUS_UART0]		= RESET(0x2d8, BIT(16)),
 	[RST_BUS_UART1]		= RESET(0x2d8, BIT(17)),
 	[RST_BUS_UART2]		= RESET(0x2d8, BIT(18)),