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| author | Tom Rini <trini@konsulko.com> | 2020-09-24 15:33:47 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-09-24 15:33:47 +0300 |
| commit | 67ece26d8b5d4bfa4fda8c456261c465d0815d7d (patch) | |
| tree | 58d6f1e224c68b9b7b710f63087cb4468394aba7 /drivers/clk | |
| parent | e119de72e3ae3accf831b5541d83d5c2faf031ff (diff) | |
| parent | 4ab3817ff16a154981f9394a2c4a0f8f6a72713b (diff) | |
| download | u-boot-67ece26d8b5d4bfa4fda8c456261c465d0815d7d.tar.xz | |
Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.01
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
bindings:
- Add binding doc for vsc8531
Diffstat (limited to 'drivers/clk')
| -rw-r--r-- | drivers/clk/clk_fixed_rate.c | 1 | ||||
| -rw-r--r-- | drivers/clk/clk_zynqmp.c | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/drivers/clk/clk_fixed_rate.c b/drivers/clk/clk_fixed_rate.c index 2c20eddb0b..55e1f8caa5 100644 --- a/drivers/clk/clk_fixed_rate.c +++ b/drivers/clk/clk_fixed_rate.c @@ -53,4 +53,5 @@ U_BOOT_DRIVER(clk_fixed_rate) = { .ofdata_to_platdata = clk_fixed_rate_ofdata_to_platdata, .platdata_auto_alloc_size = sizeof(struct clk_fixed_rate), .ops = &clk_fixed_rate_ops, + .flags = DM_FLAG_PRE_RELOC, }; diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c index 2313ac0bc0..7795119756 100644 --- a/drivers/clk/clk_zynqmp.c +++ b/drivers/clk/clk_zynqmp.c @@ -710,7 +710,7 @@ static const struct udevice_id zynqmp_clk_ids[] = { }; U_BOOT_DRIVER(zynqmp_clk) = { - .name = "zynqmp-clk", + .name = "zynqmp_clk", .id = UCLASS_CLK, .of_match = zynqmp_clk_ids, .probe = zynqmp_clk_probe, |