Merge tag 'xilinx-for-v2023.01-rc1-v3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze

Xilinx changes for v2023.01-rc1 (round 3)

fpga:
- Create new uclass
- Get rid of FPGA_DEBUG and use logging infrastructure

zynq:
- Enable early EEPROM decoding
- Some DT updates

zynqmp:
- Use OCM_BANK_0 to check config loading permission
- Change config object loading in SPL
- Some DT updates

net:
- emaclite: Enable driver for RISC-V

xilinx:
- Fix static checker warnings
- Fix GCC12 warning

sdhci:
- Read PD id from DT

1 files changed, 1 insertions, 1 deletions

diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index b2f62061ce..76fde00491 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -602,7 +602,7 @@ static void versal_get_clock_info(void)
 	}
 }
 
-int versal_clock_setup(void)
+static int versal_clock_setup(void)
 {
 	int ret;