diff options
| author | Aymen Sghaier <aymen.sghaier@nxp.com> | 2021-03-25 12:30:28 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2021-04-08 10:18:29 +0300 |
| commit | a018e6e4f7c58fe3e82d17ea552db3449c60dacc (patch) | |
| tree | 7b84771f3b6ceb770ec40f662ffc8793edd7419a /drivers/crypto/fsl/jr.c | |
| parent | 2532429b166246ef82b975435925e2772df3e70b (diff) | |
| download | u-boot-a018e6e4f7c58fe3e82d17ea552db3449c60dacc.tar.xz | |
crypto: caam: Fix pointer size to 32bit for i.MX8M
The CAAM block used in i.MX8M is 32 bits address size but when the flag
PHYS_64BIT is enabled for armv8, the CAAM driver will try to use a
wrong pointer size.
This patch fixes this issue.
Signed-off-by: Aymen Sghaier <aymen.sghaier@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/crypto/fsl/jr.c')
| -rw-r--r-- | drivers/crypto/fsl/jr.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 68954db99a..060a012eb2 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -87,13 +87,13 @@ static void jr_initregs(uint8_t sec_idx) phys_addr_t ip_base = virt_to_phys((void *)jr->input_ring); phys_addr_t op_base = virt_to_phys((void *)jr->output_ring); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(®s->irba_h, ip_base >> 32); #else sec_out32(®s->irba_h, 0x0); #endif sec_out32(®s->irba_l, (uint32_t)ip_base); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) sec_out32(®s->orba_h, op_base >> 32); #else sec_out32(®s->orba_h, 0x0); @@ -119,7 +119,7 @@ static int jr_init(uint8_t sec_idx) jr->liodn = DEFAULT_JR_LIODN; #endif jr->size = JR_SIZE; - jr->input_ring = (dma_addr_t *)memalign(ARCH_DMA_MINALIGN, + jr->input_ring = (uint32_t *)memalign(ARCH_DMA_MINALIGN, JR_SIZE * sizeof(dma_addr_t)); if (!jr->input_ring) return -1; @@ -196,7 +196,7 @@ static int jr_enqueue(uint32_t *desc_addr, uint32_t desc_word; int length = desc_len(desc_addr); int i; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #endif @@ -223,7 +223,7 @@ static int jr_enqueue(uint32_t *desc_addr, sizeof(struct jr_info), ARCH_DMA_MINALIGN); flush_dcache_range(start, end); -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Write the 64 bit Descriptor address on Input Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -272,7 +272,7 @@ static int jr_dequeue(int sec_idx) int idx, i, found; void (*callback)(uint32_t status, void *arg); void *arg = NULL; -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) uint32_t *addr_hi, *addr_lo; #else uint32_t *addr; @@ -284,7 +284,7 @@ static int jr_dequeue(int sec_idx) found = 0; phys_addr_t op_desc; - #ifdef CONFIG_PHYS_64BIT + #if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) /* Read the 64 bit Descriptor address from Output Ring. * The 32 bit hign and low part of the address will * depend on endianness of SEC block. @@ -678,7 +678,7 @@ int sec_init_idx(uint8_t sec_idx) mcr = (mcr & ~MCFGR_AWCACHE_MASK) | (0x2 << MCFGR_AWCACHE_SHIFT); #endif -#ifdef CONFIG_PHYS_64BIT +#if defined(CONFIG_PHYS_64BIT) && !defined(CONFIG_IMX8M) mcr |= (1 << MCFGR_PS_SHIFT); #endif sec_out32(&sec->mcfgr, mcr); |