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| author | Dinh Nguyen <dinguyen@kernel.org> | 2019-03-03 20:02:10 +0300 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2019-03-09 19:59:13 +0300 |
| commit | 532a54e65278564ac16878cda7146d247d8b3193 (patch) | |
| tree | a76dcbaa47389d90a8e704160517da3f8cb69653 /drivers/ddr/altera | |
| parent | e8e3f2d2d48f97b2c79b698eccedce8f4f880993 (diff) | |
| download | u-boot-532a54e65278564ac16878cda7146d247d8b3193.tar.xz | |
ARM: socfpga: fix data and tag latency values for pl310 cache controller
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Diffstat (limited to 'drivers/ddr/altera')
0 files changed, 0 insertions, 0 deletions