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| author | Tom Rini <trini@konsulko.com> | 2018-01-26 15:46:34 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-01-26 15:46:34 +0300 |
| commit | 1d12a7c8cd4e58d5c3989bc239d5fa9577079dfd (patch) | |
| tree | 00550f8c91498b648d95c0c1c9f642deb324c4a5 /drivers/ddr | |
| parent | a3f77c810b1a57853e4d5fee3014ac8cbbd03a9a (diff) | |
| parent | 58c125b9e2b232ce73ed7b24ba7b1ca5ff41c5bd (diff) | |
| download | u-boot-1d12a7c8cd4e58d5c3989bc239d5fa9577079dfd.tar.xz | |
Merge git://git.denx.de/u-boot-spi
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/microchip/ddr2.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/drivers/ddr/microchip/ddr2.c b/drivers/ddr/microchip/ddr2.c index 6056418588..a52427c3d6 100644 --- a/drivers/ddr/microchip/ddr2.c +++ b/drivers/ddr/microchip/ddr2.c @@ -57,8 +57,8 @@ static int ddr2_phy_calib_start(void) writel(SCL_START | SCL_EN, &ddr2_phy->scl_start); /* Wait for SCL for data byte to pass */ - return wait_for_bit(__func__, &ddr2_phy->scl_start, SCL_LUBPASS, - true, CONFIG_SYS_HZ, false); + return wait_for_bit_le32(&ddr2_phy->scl_start, SCL_LUBPASS, + true, CONFIG_SYS_HZ, false); } /* DDR2 Controller initialization */ @@ -256,8 +256,8 @@ void ddr2_ctrl_init(void) writel(INIT_START, &ctrl->memcon); /* wait for all host cmds to be transmitted */ - wait_for_bit(__func__, &ctrl->cmdissue, CMD_VALID, false, - CONFIG_SYS_HZ, false); + wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false, + CONFIG_SYS_HZ, false); /* inform all cmds issued, ready for normal operation */ writel(INIT_START | INIT_DONE, &ctrl->memcon); |