diff options
| author | Chris Packham <chris.packham@alliedtelesis.co.nz> | 2020-05-27 04:31:30 +0300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-07-09 07:49:44 +0300 |
| commit | 485dbd3f1088c091c32138845f2f645d51d00667 (patch) | |
| tree | f441f1c0d40303fd780d2f2b2ceed2c629337ad2 /drivers/ddr | |
| parent | 40ed88529c6ad73c20908c2c5cdbdcc01da3d476 (diff) | |
| download | u-boot-485dbd3f1088c091c32138845f2f645d51d00667.tar.xz | |
mv_ddr: ddr3: Update {min,max}_read_sample calculation
Measurements on actual hardware shown that the read ODT is early by 3
clocks. Adjust the calculation to avoid this.
Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
[upstream https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/22]
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Tested-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c index ce9a47fc2c..58ffb20507 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c +++ b/drivers/ddr/marvell/a38x/ddr3_training_hw_algo.c @@ -91,8 +91,8 @@ int ddr3_tip_write_additional_odt_setting(u32 dev_num, u32 if_id) min_read_sample = read_sample[cs_num]; } - min_read_sample = min_read_sample - 1; - max_read_sample = max_read_sample + 4 + (max_phase + 1) / 2 + 1; + min_read_sample = min_read_sample + 2; + max_read_sample = max_read_sample + 7 + (max_phase + 1) / 2 + 1; if (min_read_sample >= 0xf) min_read_sample = 0xf; if (max_read_sample >= 0x1f) |