diff options
| author | Baruch Siach <baruch@tkos.co.il> | 2020-01-20 15:20:06 +0300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2020-01-21 10:31:49 +0300 |
| commit | d67b98ed4790a30da9bdd337cfb76b03aac993e3 (patch) | |
| tree | f59122f2cbacc8a30dd3b5ca2772fcaa7cc55047 /drivers/ddr | |
| parent | c7819d409ab7671991bf906482b7adcc21266f75 (diff) | |
| download | u-boot-d67b98ed4790a30da9bdd337cfb76b03aac993e3.tar.xz | |
ddr: marvell: a38x: allow board specific clock out setup
DDR clock out might be unrelated to the number of active chip-select.
For example, the board might have two DDR components, but only one
chip-select. The clk_enable mask allows the board to enable DDR clocks
regardless of active chip-selects.
Reviewed-by: Stefan Roese <sr@denx.de>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Diffstat (limited to 'drivers/ddr')
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr3_training.c | 10 | ||||
| -rw-r--r-- | drivers/ddr/marvell/a38x/ddr_topology_def.h | 3 |
2 files changed, 11 insertions, 2 deletions
diff --git a/drivers/ddr/marvell/a38x/ddr3_training.c b/drivers/ddr/marvell/a38x/ddr3_training.c index c7be700d64..9718f18c30 100644 --- a/drivers/ddr/marvell/a38x/ddr3_training.c +++ b/drivers/ddr/marvell/a38x/ddr3_training.c @@ -280,8 +280,14 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) { u32 data, addr_hi, data_high; u32 mem_index; + u32 clk_enable; struct mv_ddr_topology_map *tm = mv_ddr_topology_map_get(); + if (tm->clk_enable & (1 << cs_num)) + clk_enable = 1; + else + clk_enable = enable; + if (enable == 1) { data = (tm->interface_params[if_id].bus_width == MV_DDR_DEV_WIDTH_8BIT) ? 0 : 1; @@ -316,13 +322,13 @@ int ddr3_tip_configure_cs(u32 dev_num, u32 if_id, u32 cs_num, u32 enable) case 2: CHECK_STATUS(ddr3_tip_if_write (dev_num, ACCESS_TYPE_UNICAST, if_id, - DUNIT_CTRL_LOW_REG, (enable << (cs_num + 11)), + DUNIT_CTRL_LOW_REG, (clk_enable << (cs_num + 11)), 1 << (cs_num + 11))); break; case 3: CHECK_STATUS(ddr3_tip_if_write (dev_num, ACCESS_TYPE_UNICAST, if_id, - DUNIT_CTRL_LOW_REG, (enable << 15), 1 << 15)); + DUNIT_CTRL_LOW_REG, (clk_enable << 15), 1 << 15)); break; } diff --git a/drivers/ddr/marvell/a38x/ddr_topology_def.h b/drivers/ddr/marvell/a38x/ddr_topology_def.h index e6fe8a0428..950f296ff9 100644 --- a/drivers/ddr/marvell/a38x/ddr_topology_def.h +++ b/drivers/ddr/marvell/a38x/ddr_topology_def.h @@ -124,6 +124,9 @@ struct mv_ddr_topology_map { /* electrical parameters */ unsigned int electrical_data[MV_DDR_EDATA_LAST]; + + /* Clock enable mask */ + u32 clk_enable; }; enum mv_ddr_iface_mode { |