diff options
| author | Peng Fan <peng.fan@nxp.com> | 2020-05-04 17:09:00 +0300 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2020-05-10 21:55:20 +0300 |
| commit | 39320e7256412ed4b6eee9fc09f7d30f0e4ddee4 (patch) | |
| tree | b2fcc6f20a7b84d1cafacdc35b33a04440e4279d /drivers/dma | |
| parent | f290fe0a4291a6251358aaca7a3f25964f0e12da (diff) | |
| download | u-boot-39320e7256412ed4b6eee9fc09f7d30f0e4ddee4.tar.xz | |
mtd: nand: support GPMI NAND driver for i.MX8
enable the GPMI NAND driver for i.MX8, i.MX8 use similar controller as
i.MX8M
- register definition for i.mx8
- DMA structure must be 32bit address
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'drivers/dma')
| -rw-r--r-- | drivers/dma/Kconfig | 2 | ||||
| -rw-r--r-- | drivers/dma/apbh_dma.c | 13 |
2 files changed, 9 insertions, 6 deletions
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig index 655e79fbaf..1993c1d31d 100644 --- a/drivers/dma/Kconfig +++ b/drivers/dma/Kconfig @@ -44,7 +44,7 @@ config TI_EDMA3 config APBH_DMA bool "Support APBH DMA" - depends on MX23 || MX28 || MX6 || MX7 || IMX8M + depends on MX23 || MX28 || MX6 || MX7 || IMX8 || IMX8M help Enable APBH DMA driver. diff --git a/drivers/dma/apbh_dma.c b/drivers/dma/apbh_dma.c index 8d17f8f01d..69eb040d32 100644 --- a/drivers/dma/apbh_dma.c +++ b/drivers/dma/apbh_dma.c @@ -7,6 +7,8 @@ * * Based on code from LTIB: * Copyright (C) 2010 Freescale Semiconductor, Inc. All Rights Reserved. + * Copyright 2017 NXP + * */ #include <cpu_func.h> @@ -88,7 +90,7 @@ void mxs_dma_flush_desc(struct mxs_dma_desc *desc) uint32_t addr; uint32_t size; - addr = (uint32_t)desc; + addr = (uintptr_t)desc; size = roundup(sizeof(struct mxs_dma_desc), MXS_DMA_ALIGNMENT); flush_dcache_range(addr, addr + size); @@ -215,16 +217,17 @@ static int mxs_dma_reset(int channel) #if defined(CONFIG_MX23) uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_ctrl0_set); uint32_t offset = APBH_CTRL0_RESET_CHANNEL_OFFSET; -#elif (defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || defined(CONFIG_IMX8M)) - uint32_t setreg = (uint32_t)(&apbh_regs->hw_apbh_channel_ctrl_set); - uint32_t offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; +#elif defined(CONFIG_MX28) || defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ + defined(CONFIG_IMX8) || defined(CONFIG_IMX8M) + u32 setreg = (uintptr_t)(&apbh_regs->hw_apbh_channel_ctrl_set); + u32 offset = APBH_CHANNEL_CTRL_RESET_CHANNEL_OFFSET; #endif ret = mxs_dma_validate_chan(channel); if (ret) return ret; - writel(1 << (channel + offset), setreg); + writel(1 << (channel + offset), (uintptr_t)setreg); return 0; } |