diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-08 05:38:20 +0300 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 16:38:33 +0300 |
| commit | db5741f7a85ec3ee79b64496172afaa7dc2cb225 (patch) | |
| tree | 20f749d41ff3c329758f16c1a67f9c5772f35278 /drivers/fpga | |
| parent | bb25aca1343304e0334e9eebfb9d350eaf276882 (diff) | |
| download | u-boot-db5741f7a85ec3ee79b64496172afaa7dc2cb225.tar.xz | |
arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get system manager base address from DT node instead of
using #define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'drivers/fpga')
| -rw-r--r-- | drivers/fpga/socfpga_arria10.c | 7 | ||||
| -rw-r--r-- | drivers/fpga/socfpga_gen5.c | 4 |
2 files changed, 3 insertions, 8 deletions
diff --git a/drivers/fpga/socfpga_arria10.c b/drivers/fpga/socfpga_arria10.c index 5fb9d6a191..2853581b97 100644 --- a/drivers/fpga/socfpga_arria10.c +++ b/drivers/fpga/socfpga_arria10.c @@ -30,9 +30,6 @@ DECLARE_GLOBAL_DATA_PTR; static const struct socfpga_fpga_manager *fpga_manager_base = (void *)SOCFPGA_FPGAMGRREGS_ADDRESS; -static const struct socfpga_system_manager *system_manager_base = - (void *)SOCFPGA_SYSMGR_ADDRESS; - static void fpgamgr_set_cd_ratio(unsigned long ratio); static uint32_t fpgamgr_get_msel(void) @@ -818,7 +815,7 @@ int socfpga_loadfs(fpga_fs_info *fpga_fsinfo, const void *buf, size_t bsize, } /* Disable all signals from HPS peripheral controller to FPGA */ - writel(0, &system_manager_base->fpgaintf_en_global); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL); /* Disable all axi bridges (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); @@ -910,7 +907,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) memset(&rbfinfo, 0, sizeof(rbfinfo)); /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &system_manager_base->fpgaintf_en_global); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_FPGAINTF_EN_GLOBAL); /* Disable all axi bridge (hps2fpga, lwhps2fpga & fpga2hps) */ socfpga_bridges_reset(); diff --git a/drivers/fpga/socfpga_gen5.c b/drivers/fpga/socfpga_gen5.c index 6d16e0b37f..d73474f29e 100644 --- a/drivers/fpga/socfpga_gen5.c +++ b/drivers/fpga/socfpga_gen5.c @@ -15,8 +15,6 @@ static struct socfpga_fpga_manager *fpgamgr_regs = (struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS; -static struct socfpga_system_manager *sysmgr_regs = - (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS; /* Set CD ratio */ static void fpgamgr_set_cd_ratio(unsigned long ratio) @@ -214,7 +212,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size) /* Prior programming the FPGA, all bridges need to be shut off */ /* Disable all signals from hps peripheral controller to fpga */ - writel(0, &sysmgr_regs->fpgaintfgrp_module); + writel(0, socfpga_get_sysmgr_addr() + SYSMGR_GEN5_FPGAINFGRP_MODULE); /* Disable all signals from FPGA to HPS SDRAM */ #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080 |