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author | Tom Rini <trini@konsulko.com> | 2016-06-04 19:12:26 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2016-06-04 19:12:26 +0300 |
commit | cc749523ae1adec3856f2b7fe77a6d856da4652a (patch) | |
tree | d386320f6f69ead4a461619dd8348347ae7cc7dd /drivers/gpio/Kconfig | |
parent | 8aa57a95a2efc8174c5482f9b3abc4920b479ff2 (diff) | |
parent | 23d4e5ba49b878e01321be2af4e94f73389f4958 (diff) | |
download | u-boot-cc749523ae1adec3856f2b7fe77a6d856da4652a.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-mpc85xx
Diffstat (limited to 'drivers/gpio/Kconfig')
-rw-r--r-- | drivers/gpio/Kconfig | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig index 32219ed478..73b862dc0b 100644 --- a/drivers/gpio/Kconfig +++ b/drivers/gpio/Kconfig @@ -188,4 +188,30 @@ config DM_PCA953X Now, max 24 bits chips and PCA953X compatible chips are supported + +config MPC85XX_GPIO + bool "Freescale MPC85XX GPIO driver" + depends on DM_GPIO + help + This driver supports the built-in GPIO controller of MPC85XX CPUs. + Each GPIO bank is identified by its own entry in the device tree, + i.e. + + gpio-controller@fc00 { + #gpio-cells = <2>; + compatible = "fsl,pq3-gpio"; + reg = <0xfc00 0x100> + } + + By default, each bank is assumed to have 32 GPIOs, but the ngpios + setting is honored, so the number of GPIOs for each bank is + configurable to match the actual GPIO count of the SoC (e.g. the + 32/32/23 banks of the P1022 SoC). + + Aside from the standard functions of input/output mode, and output + value setting, the open-drain feature, which can configure individual + GPIOs to work as open-drain outputs, is supported. + + The driver has been tested on MPC85XX, but it is likely that other + PowerQUICC III devices will work as well. endmenu |