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authorBin Meng <bmeng.cn@gmail.com>2021-02-25 12:22:50 +0300
committerPriyanka Jain <priyanka.jain@nxp.com>2021-03-05 07:55:43 +0300
commit271a87b4ecc498cf718738b1a5271c911eec17ff (patch)
tree6b1aaf46db033f6d9f05df17580b93895d8463bd /drivers/gpio
parentf94cbb5b87e19ad4316966b581bd40f70ee80c93 (diff)
downloadu-boot-271a87b4ecc498cf718738b1a5271c911eec17ff.tar.xz
gpio: mpc8xxx: Support controller register physical address beyond 32-bit
dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Diffstat (limited to 'drivers/gpio')
-rw-r--r--drivers/gpio/mpc8xxx_gpio.c7
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/gpio/mpc8xxx_gpio.c b/drivers/gpio/mpc8xxx_gpio.c
index c733603289..f7ffd8926a 100644
--- a/drivers/gpio/mpc8xxx_gpio.c
+++ b/drivers/gpio/mpc8xxx_gpio.c
@@ -20,7 +20,7 @@ struct mpc8xxx_gpio_data {
/* The bank's register base in memory */
struct ccsr_gpio __iomem *base;
/* The address of the registers; used to identify the bank */
- ulong addr;
+ phys_addr_t addr;
/* The GPIO count of the bank */
uint gpio_count;
/* The GPDAT register cannot be used to determine the value of output
@@ -181,7 +181,7 @@ static int mpc8xxx_gpio_of_to_plat(struct udevice *dev)
if (dev_read_bool(dev, "little-endian"))
data->little_endian = true;
- plat->addr = (ulong)dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
+ plat->addr = dev_read_addr_size_index(dev, 0, (fdt_size_t *)&plat->size);
plat->ngpios = dev_read_u32_default(dev, "ngpios", 32);
return 0;
@@ -220,7 +220,8 @@ static int mpc8xxx_gpio_probe(struct udevice *dev)
mpc8xxx_gpio_plat_to_priv(dev);
- snprintf(name, sizeof(name), "MPC@%lx_", data->addr);
+ snprintf(name, sizeof(name), "MPC@%.8llx",
+ (unsigned long long)data->addr);
str = strdup(name);
if (!str)