diff options
| author | Siew Chin Lim <elly.siew.chin.lim@intel.com> | 2020-12-24 13:21:03 +0300 |
|---|---|---|
| committer | Ley Foon Tan <ley.foon.tan@intel.com> | 2021-01-15 12:48:36 +0300 |
| commit | d456dfbaa0d8e43991791723cbcd0b9def95fd8d (patch) | |
| tree | f0611d062687e25e4d47aa8d84ff2a69bf71261b /drivers/mmc/ca_dw_mmc.c | |
| parent | 2e54a1d46c143f12653a44c8485e7d8bfd573b1d (diff) | |
| download | u-boot-d456dfbaa0d8e43991791723cbcd0b9def95fd8d.tar.xz | |
mmc: dwmmc: Change designware MMC 'clksel' callback function to return status
Change 'clksel' callback function to allow the code to return a
status.
This patch is a preparation for enabling Arm-Trusted-Firmware (ATF)
in Intel SoC FPGA. This patch does not change functionality.
When using Arm-Trusted-Firmware (ATF) in Intel SoC FPGA, the MMC clock
related register is secure register which is required to be written
via SMC/PCSI call. It is possible that U-Boot fail to write the
register if there is unexpected error between U-Boot and ATF.
As a result, there maybe signal integrity on MMC connection due to
clock. So, the code should reports error to user when 'clksel' fail.
Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Diffstat (limited to 'drivers/mmc/ca_dw_mmc.c')
| -rw-r--r-- | drivers/mmc/ca_dw_mmc.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/mmc/ca_dw_mmc.c b/drivers/mmc/ca_dw_mmc.c index fad2ff5aaf..2b79356a20 100644 --- a/drivers/mmc/ca_dw_mmc.c +++ b/drivers/mmc/ca_dw_mmc.c @@ -40,7 +40,7 @@ struct ca_dwmmc_priv_data { u8 ds; }; -static void ca_dwmci_clksel(struct dwmci_host *host) +static int ca_dwmci_clksel(struct dwmci_host *host) { struct ca_dwmmc_priv_data *priv = host->priv; u32 val = readl(priv->sd_dll_reg); @@ -52,6 +52,8 @@ static void ca_dwmci_clksel(struct dwmci_host *host) val |= SD_CLK_SEL_100MHZ; writel(val, priv->sd_dll_reg); + + return 0; } static void ca_dwmci_board_init(struct dwmci_host *host) |