diff options
| author | Kishon Vijay Abraham I <kishon@ti.com> | 2018-01-30 18:01:34 +0300 |
|---|---|---|
| committer | Jaehoon Chung <jh80.chung@samsung.com> | 2018-02-19 10:58:54 +0300 |
| commit | 9b3fc21837dc32eda9656f264f74719ea77311a2 (patch) | |
| tree | 066b0b655cabb565d1ed4e67a0869d8940f4dc82 /drivers/mmc/omap_hsmmc.c | |
| parent | 8fc238bfada16d61dee4240de2d49f38a6a6f941 (diff) | |
| download | u-boot-9b3fc21837dc32eda9656f264f74719ea77311a2.tar.xz | |
mmc: omap_hsmmc: Enable DDR mode support
In order to enable DDR mode, Dual Data Rate mode bit has to be set in
MMCHS_CON register. Set it here.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Diffstat (limited to 'drivers/mmc/omap_hsmmc.c')
| -rw-r--r-- | drivers/mmc/omap_hsmmc.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/omap_hsmmc.c b/drivers/mmc/omap_hsmmc.c index c6b74a1263..2f4909e34b 100644 --- a/drivers/mmc/omap_hsmmc.c +++ b/drivers/mmc/omap_hsmmc.c @@ -271,6 +271,11 @@ static void omap_hsmmc_set_timing(struct mmc *mmc) val &= ~AC12_UHSMC_MASK; priv->mode = mmc->selected_mode; + if (mmc_is_mode_ddr(priv->mode)) + writel(readl(&mmc_base->con) | DDR, &mmc_base->con); + else + writel(readl(&mmc_base->con) & ~DDR, &mmc_base->con); + switch (priv->mode) { case MMC_HS_200: case UHS_SDR104: |