diff options
| author | Ley Foon Tan <ley.foon.tan@intel.com> | 2019-11-08 05:38:21 +0300 |
|---|---|---|
| committer | Marek Vasut <marex@denx.de> | 2020-01-07 16:38:33 +0300 |
| commit | 94172c7961124a4abf1aeedb1705a88a77744103 (patch) | |
| tree | 1a6756077070c3dba1861bceb1af27ad5a17b0f3 /drivers/mmc/socfpga_dw_mmc.c | |
| parent | db5741f7a85ec3ee79b64496172afaa7dc2cb225 (diff) | |
| download | u-boot-94172c7961124a4abf1aeedb1705a88a77744103.tar.xz | |
arm: socfpga: Convert clock manager from struct to defines
Convert clock manager for Gen5, Arria 10 and Stratix 10 from struct
to defines.
Change to get clock manager base address from DT node instead of using
#define.
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'drivers/mmc/socfpga_dw_mmc.c')
| -rw-r--r-- | drivers/mmc/socfpga_dw_mmc.c | 11 |
1 files changed, 4 insertions, 7 deletions
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c index df9e8ccb1e..568a3e77d3 100644 --- a/drivers/mmc/socfpga_dw_mmc.c +++ b/drivers/mmc/socfpga_dw_mmc.c @@ -18,9 +18,6 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_clock_manager *clock_manager_base = - (void *)SOCFPGA_CLKMGR_ADDRESS; - struct socfpga_dwmci_plat { struct mmc_config cfg; struct mmc mmc; @@ -54,8 +51,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) ((priv->drvsel & 0x7) << SYSMGR_SDMMC_DRVSEL_SHIFT); /* Disable SDMMC clock. */ - clrbits_le32(&clock_manager_base->per_pll.en, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + clrbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); debug("%s: drvsel %d smplsel %d\n", __func__, priv->drvsel, priv->smplsel); @@ -65,8 +62,8 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host) readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC)); /* Enable SDMMC clock */ - setbits_le32(&clock_manager_base->per_pll.en, - CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); + setbits_le32(socfpga_get_clkmgr_addr() + CLKMGR_PERPLL_EN, + CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK); } static int socfpga_dwmmc_get_clk_rate(struct udevice *dev) |