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authorLey Foon Tan <ley.foon.tan@intel.com>2019-11-08 05:38:20 +0300
committerMarek Vasut <marex@denx.de>2020-01-07 16:38:33 +0300
commitdb5741f7a85ec3ee79b64496172afaa7dc2cb225 (patch)
tree20f749d41ff3c329758f16c1a67f9c5772f35278 /drivers/mmc/socfpga_dw_mmc.c
parentbb25aca1343304e0334e9eebfb9d350eaf276882 (diff)
downloadu-boot-db5741f7a85ec3ee79b64496172afaa7dc2cb225.tar.xz
arm: socfpga: Convert system manager from struct to defines
Convert system manager for Gen5, Arria 10 and Stratix 10 from struct to defines. Change to get system manager base address from DT node instead of using #define. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Diffstat (limited to 'drivers/mmc/socfpga_dw_mmc.c')
-rw-r--r--drivers/mmc/socfpga_dw_mmc.c6
1 files changed, 2 insertions, 4 deletions
diff --git a/drivers/mmc/socfpga_dw_mmc.c b/drivers/mmc/socfpga_dw_mmc.c
index 739c1629a2..df9e8ccb1e 100644
--- a/drivers/mmc/socfpga_dw_mmc.c
+++ b/drivers/mmc/socfpga_dw_mmc.c
@@ -20,8 +20,6 @@ DECLARE_GLOBAL_DATA_PTR;
static const struct socfpga_clock_manager *clock_manager_base =
(void *)SOCFPGA_CLKMGR_ADDRESS;
-static const struct socfpga_system_manager *system_manager_base =
- (void *)SOCFPGA_SYSMGR_ADDRESS;
struct socfpga_dwmci_plat {
struct mmc_config cfg;
@@ -61,10 +59,10 @@ static void socfpga_dwmci_clksel(struct dwmci_host *host)
debug("%s: drvsel %d smplsel %d\n", __func__,
priv->drvsel, priv->smplsel);
- writel(sdmmc_mask, &system_manager_base->sdmmcgrp_ctrl);
+ writel(sdmmc_mask, socfpga_get_sysmgr_addr() + SYSMGR_SDMMC);
debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
- readl(&system_manager_base->sdmmcgrp_ctrl));
+ readl(socfpga_get_sysmgr_addr() + SYSMGR_SDMMC));
/* Enable SDMMC clock */
setbits_le32(&clock_manager_base->per_pll.en,