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authorMarek Vasut <marek.vasut+renesas@gmail.com>2019-01-12 01:45:54 +0300
committerMarek Vasut <marex@denx.de>2019-02-09 13:08:40 +0300
commit992bcf4f27794a7f578e0145ef1c933a87a1d83c (patch)
tree837329bf68abe3870eef2c7697fd261bee7db128 /drivers/mmc/tmio-common.h
parent97276a91db8e98f081a40ddf9dc8f81d4032a756 (diff)
downloadu-boot-992bcf4f27794a7f578e0145ef1c933a87a1d83c.tar.xz
mmc: tmio: Make DMA transfer end bit configurable
Different versions of the SDHI core use either bit 17 or bit 20 for the DTRAEND indication, which can differ even between SoC revisions. Make the DTRAEND bit position part of the driver private data, so that the probe function can set this accordingly. Set this to 20 on Socionext SoCs and either 17 or 20 on Renesas SoCs, depending on the SoC. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Diffstat (limited to 'drivers/mmc/tmio-common.h')
-rw-r--r--drivers/mmc/tmio-common.h1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/mmc/tmio-common.h b/drivers/mmc/tmio-common.h
index 192026ce3e..58ce3d65b0 100644
--- a/drivers/mmc/tmio-common.h
+++ b/drivers/mmc/tmio-common.h
@@ -119,6 +119,7 @@ struct tmio_sd_priv {
void __iomem *regbase;
unsigned int version;
u32 caps;
+ u32 read_poll_flag;
#define TMIO_SD_CAP_NONREMOVABLE BIT(0) /* Nonremovable e.g. eMMC */
#define TMIO_SD_CAP_DMA_INTERNAL BIT(1) /* have internal DMA engine */
#define TMIO_SD_CAP_DIV1024 BIT(2) /* divisor 1024 is available */