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| author | Sean Anderson <sean.anderson@seco.com> | 2021-11-23 23:03:47 +0300 |
|---|---|---|
| committer | Jaehoon Chung <jh80.chung@samsung.com> | 2022-01-12 03:56:40 +0300 |
| commit | b2acee4bb02672b5bf2b0f4a6f77b0e5ddc9d6b5 (patch) | |
| tree | 2d5a8a3d22818a056bc9382716a0d0f3cf781ae4 /drivers/mmc | |
| parent | 00e0cd7fda11d5c508a3fc0c65b8d06d672bb1a0 (diff) | |
| download | u-boot-b2acee4bb02672b5bf2b0f4a6f77b0e5ddc9d6b5.tar.xz | |
mmc: fsl_esdhc_imx: set sysctl register for clock initialization
[ fsl_esdhc commit 263ddfc3454ead3a988adef39b962479adce2b28 ]
The initial clock setting should be through sysctl register only,
while the mmc_set_clock() will call mmc_set_ios() introduce other
configurations like bus width, mode, and so on.
Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/fsl_esdhc_imx.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 25e912ba95..9299635f50 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1020,7 +1020,7 @@ static int esdhc_init_common(struct fsl_esdhc_priv *priv, struct mmc *mmc) esdhc_setbits32(®s->sysctl, SYSCTL_HCKEN | SYSCTL_IPGEN); /* Set the initial clock speed */ - mmc_set_clock(mmc, 400000, MMC_CLK_ENABLE); + set_sysctl(priv, mmc, 400000); /* Disable the BRR and BWR bits in IRQSTAT */ esdhc_clrbits32(®s->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR); |