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| author | Ashok Reddy Soma <ashok.reddy.soma@amd.com> | 2022-09-30 12:25:46 +0300 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2022-10-05 12:36:54 +0300 |
| commit | cbdee4d5e88c8509a3491f8784be42841466cb6c (patch) | |
| tree | e5fc029da034ffeba407157e73be0738c9a83962 /drivers/mmc | |
| parent | 9a082d2548de523c37f035cee7e0c280bad62bee (diff) | |
| download | u-boot-cbdee4d5e88c8509a3491f8784be42841466cb6c.tar.xz | |
mmc: zynq_sdhci: Change node_id prototype to u32
In Versal platform power domain node_id is bigger than u8, hence
change prototype to u32 to accommodate. Change u8 to u32 in the function
prototypes that use node_id and remove casting to u32 from
xilinx_pm_request() call parameters.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Link: https://lore.kernel.org/r/20220930092548.18453-2-ashok.reddy.soma@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/zynq_sdhci.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index 8f4071c8c2..3a4194452c 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -111,7 +111,7 @@ static const u8 mode2timing[] = { [MMC_HS_200] = MMC_TIMING_MMC_HS200, }; -static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay) +static inline int arasan_zynqmp_set_in_tapdelay(u32 node_id, u32 itap_delay) { int ret; @@ -155,7 +155,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay) if (ret) return ret; } else { - return xilinx_pm_request(PM_IOCTL, (u32)node_id, + return xilinx_pm_request(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, PM_TAPDELAY_INPUT, itap_delay, NULL); } @@ -163,7 +163,7 @@ static inline int arasan_zynqmp_set_in_tapdelay(u8 node_id, u32 itap_delay) return 0; } -static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay) +static inline int arasan_zynqmp_set_out_tapdelay(u32 node_id, u32 otap_delay) { if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { if (node_id == NODE_SD_0) @@ -174,13 +174,13 @@ static inline int arasan_zynqmp_set_out_tapdelay(u8 node_id, u32 otap_delay) return zynqmp_mmio_write(SD_OTAP_DLY, SD1_OTAPDLYSEL_MASK, (otap_delay << 16)); } else { - return xilinx_pm_request(PM_IOCTL, (u32)node_id, + return xilinx_pm_request(PM_IOCTL, node_id, IOCTL_SET_SD_TAPDELAY, PM_TAPDELAY_OUTPUT, otap_delay, NULL); } } -static inline int zynqmp_dll_reset(u8 node_id, u32 type) +static inline int zynqmp_dll_reset(u32 node_id, u32 type) { if (IS_ENABLED(CONFIG_SPL_BUILD) || current_el() == 3) { if (node_id == NODE_SD_0) @@ -192,12 +192,12 @@ static inline int zynqmp_dll_reset(u8 node_id, u32 type) type == PM_DLL_RESET_ASSERT ? SD1_DLL_RST : 0); } else { - return xilinx_pm_request(PM_IOCTL, (u32)node_id, + return xilinx_pm_request(PM_IOCTL, node_id, IOCTL_SD_DLL_RESET, type, 0, NULL); } } -static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 node_id) +static int arasan_zynqmp_dll_reset(struct sdhci_host *host, u32 node_id) { struct mmc *mmc = (struct mmc *)host->mmc; struct udevice *dev = mmc->dev; |