diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2021-04-20 11:37:10 +0300 |
|---|---|---|
| committer | Peng Fan <peng.fan@nxp.com> | 2021-06-22 07:01:52 +0300 |
| commit | 3a3672cc3769a43750dd9fea90ed7a7900cb227f (patch) | |
| tree | 17108ca3d865c3b2fb9e2b98f29c2e3ed400584d /drivers/mmc | |
| parent | 97c8cb524c19f054036efd2b4429273bd503e39c (diff) | |
| download | u-boot-3a3672cc3769a43750dd9fea90ed7a7900cb227f.tar.xz | |
mmc: mtk-sd: increase the minimum bus frequency
With a 48MHz input clock, the lowest bus frequency can be as low as
48000000 / (4 * 4095) = 2930Hz. Such an extremely low frequency will cause
the mmc framework take seconds to finish the initialization.
Limiting the minimum bus frequency to a slightly higher value can solve the
issue without any side effects.
Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/mmc')
| -rw-r--r-- | drivers/mmc/mtk-sd.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c index 48a764be82..8599f095bc 100644 --- a/drivers/mmc/mtk-sd.c +++ b/drivers/mmc/mtk-sd.c @@ -232,6 +232,8 @@ #define SCLK_CYCLES_SHIFT 20 +#define MIN_BUS_CLK 200000 + #define CMD_INTS_MASK \ (MSDC_INT_CMDRDY | MSDC_INT_RSPCRCERR | MSDC_INT_CMDTMO) @@ -1639,6 +1641,9 @@ static int msdc_drv_probe(struct udevice *dev) else cfg->f_min = host->src_clk_freq / (4 * 4095); + if (cfg->f_min < MIN_BUS_CLK) + cfg->f_min = MIN_BUS_CLK; + if (cfg->f_max < cfg->f_min || cfg->f_max > host->src_clk_freq) cfg->f_max = host->src_clk_freq; |