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authorTom Rini <trini@konsulko.com>2021-09-16 17:29:40 +0300
committerTom Rini <trini@konsulko.com>2021-09-16 17:29:40 +0300
commit6674edaabfd271471608146806f5b6540bc76a1b (patch)
tree574f8b5265002ad046aa1b81725a9483feb48a8d /drivers/mmc
parent4f8bf67f9c7fec8c5c1ae57c6ba24d337a19c578 (diff)
parentbb92678ced0b1594b93ab2f10b2c17750c789c96 (diff)
downloadu-boot-6674edaabfd271471608146806f5b6540bc76a1b.tar.xz
Merge tag 'v2021.10-rc4' into next
Prepare v2021.10-rc4 Signed-off-by: Tom Rini <trini@konsulko.com> # gpg: Signature made Tue 14 Sep 2021 06:58:32 PM EDT # gpg: using RSA key 1A3C7F70E08FAB1707809BBF147C39FF9634B72C # gpg: Good signature from "Thomas Rini <trini@konsulko.com>" [ultimate] # Conflicts: # board/Arcturus/ucp1020/spl.c # cmd/mvebu/Kconfig # common/Kconfig.boot # common/image-fit.c # configs/UCP1020_defconfig # configs/sifive_unmatched_defconfig # drivers/pci/Kconfig # include/configs/UCP1020.h # include/configs/sifive-unmatched.h # lib/Makefile # scripts/config_whitelist.txt
Diffstat (limited to 'drivers/mmc')
-rw-r--r--drivers/mmc/fsl_esdhc.c7
-rw-r--r--drivers/mmc/mmc-uclass.c5
-rw-r--r--drivers/mmc/mmc.c32
-rw-r--r--drivers/mmc/sdhci.c3
-rw-r--r--drivers/mmc/sunxi_mmc.c10
5 files changed, 39 insertions, 18 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 1d98fa65c4..ebb307e950 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -361,13 +361,6 @@ static int esdhc_send_cmd_common(struct fsl_esdhc_priv *priv, struct mmc *mmc,
while (esdhc_read32(&regs->prsstat) & PRSSTAT_DLA)
;
- /* Wait at least 8 SD clock cycles before the next command */
- /*
- * Note: This is way more than 8 cycles, but 1ms seems to
- * resolve timing issues with some cards
- */
- udelay(1000);
-
/* Set up for a data transfer if we have one */
if (data) {
err = esdhc_setup_data(priv, mmc, data);
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 0e13238c7e..3ee92d03ca 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -342,6 +342,9 @@ void mmc_do_preinit(void)
if (!m)
continue;
+
+ m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
+
if (m->preinit)
mmc_start_init(m);
}
@@ -414,7 +417,7 @@ int mmc_bind(struct udevice *dev, struct mmc *mmc, const struct mmc_config *cfg)
/* setup initial part type */
bdesc->part_type = cfg->part_type;
mmc->dev = dev;
-
+ mmc->user_speed_mode = MMC_MODES_END;
return 0;
}
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 8078a89f18..d3babbfeb1 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -823,7 +823,7 @@ static int __mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value,
* capable of polling by using mmc_wait_dat0, then rely on waiting the
* stated timeout to be sufficient.
*/
- if (ret == -ENOSYS && !send_status) {
+ if (ret == -ENOSYS || !send_status) {
mdelay(timeout_ms);
return 0;
}
@@ -2092,14 +2092,16 @@ static int mmc_select_mode_and_width(struct mmc *mmc, uint card_caps)
}
#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT) || \
- CONFIG_IS_ENABLED(MMC_HS400_SUPPORT)
+ CONFIG_IS_ENABLED(MMC_HS400_SUPPORT) || \
+ CONFIG_IS_ENABLED(MMC_HS400_ES_SUPPORT)
/*
* In case the eMMC is in HS200/HS400 mode, downgrade to HS mode
* before doing anything else, since a transition from either of
* the HS200/HS400 mode directly to legacy mode is not supported.
*/
if (mmc->selected_mode == MMC_HS_200 ||
- mmc->selected_mode == MMC_HS_400)
+ mmc->selected_mode == MMC_HS_400 ||
+ mmc->selected_mode == MMC_HS_400_ES)
mmc_set_card_speed(mmc, MMC_HS, true);
else
#endif
@@ -2862,7 +2864,25 @@ int mmc_start_init(struct mmc *mmc)
* timings.
*/
mmc->host_caps = mmc->cfg->host_caps | MMC_CAP(MMC_LEGACY) |
- MMC_CAP(MMC_LEGACY) | MMC_MODE_1BIT;
+ MMC_MODE_1BIT;
+
+ if (IS_ENABLED(CONFIG_MMC_SPEED_MODE_SET)) {
+ if (mmc->user_speed_mode != MMC_MODES_END) {
+ int i;
+ /* set host caps */
+ if (mmc->host_caps & MMC_CAP(mmc->user_speed_mode)) {
+ /* Remove all existing speed capabilities */
+ for (i = MMC_LEGACY; i < MMC_MODES_END; i++)
+ mmc->host_caps &= ~MMC_CAP(i);
+ mmc->host_caps |= (MMC_CAP(mmc->user_speed_mode)
+ | MMC_CAP(MMC_LEGACY) |
+ MMC_MODE_1BIT);
+ } else {
+ pr_err("bus_mode requested is not supported\n");
+ return -EINVAL;
+ }
+ }
+ }
#if CONFIG_IS_ENABLED(DM_MMC)
mmc_deferred_probe(mmc);
#endif
@@ -2952,7 +2972,7 @@ int mmc_deinit(struct mmc *mmc)
return sd_select_mode_and_width(mmc, caps_filtered);
} else {
caps_filtered = mmc->card_caps &
- ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400));
+ ~(MMC_CAP(MMC_HS_200) | MMC_CAP(MMC_HS_400) | MMC_CAP(MMC_HS_400_ES));
return mmc_select_mode_and_width(mmc, caps_filtered);
}
@@ -3060,6 +3080,8 @@ int mmc_init_device(int num)
}
m = mmc_get_mmc_dev(dev);
+ m->user_speed_mode = MMC_MODES_END; /* Initialising user set speed mode */
+
if (!m)
return 0;
if (m->preinit)
diff --git a/drivers/mmc/sdhci.c b/drivers/mmc/sdhci.c
index 2f78da61be..03bfd9d18a 100644
--- a/drivers/mmc/sdhci.c
+++ b/drivers/mmc/sdhci.c
@@ -258,8 +258,7 @@ static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
flags = SDHCI_CMD_RESP_LONG;
else if (cmd->resp_type & MMC_RSP_BUSY) {
flags = SDHCI_CMD_RESP_SHORT_BUSY;
- if (data)
- mask |= SDHCI_INT_DATA_END;
+ mask |= SDHCI_INT_DATA_END;
} else
flags = SDHCI_CMD_RESP_SHORT;
diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
index 178b8cf106..aaab0cf866 100644
--- a/drivers/mmc/sunxi_mmc.c
+++ b/drivers/mmc/sunxi_mmc.c
@@ -349,10 +349,14 @@ static int mmc_trans_data_by_cpu(struct sunxi_mmc_priv *priv, struct mmc *mmc,
* register without checking the status register after every
* read. That saves half of the costly MMIO reads, effectively
* doubling the read performance.
+ * Some SoCs (A20) report a level of 0 if the FIFO is
+ * completely full (value masked out?). Use a safe minimal
+ * FIFO size in this case.
*/
- for (in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
- in_fifo > 0;
- in_fifo--)
+ in_fifo = SUNXI_MMC_STATUS_FIFO_LEVEL(status);
+ if (in_fifo == 0 && (status & SUNXI_MMC_STATUS_FIFO_FULL))
+ in_fifo = 32;
+ for (; in_fifo > 0; in_fifo--)
buff[i++] = readl_relaxed(&priv->reg->fifo);
dmb();
}