diff options
author | Tom Rini <trini@konsulko.com> | 2019-04-14 07:03:06 +0300 |
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committer | Tom Rini <trini@konsulko.com> | 2019-04-14 07:03:06 +0300 |
commit | 216800acf1fbf9f498455bf3c92d4513d9a4c681 (patch) | |
tree | 08ee65c9c73a954c71b6f6051725338f0f23fdcb /drivers/mtd | |
parent | cf5eebeb18f7790d5030eb94f51fca0ebcd6e406 (diff) | |
parent | 59aea29a31869ed0fd5ffc4b95050db966fcaf6d (diff) | |
download | u-boot-216800acf1fbf9f498455bf3c92d4513d9a4c681.tar.xz |
Merge branch 'master' of git://git.denx.de/u-boot-spi
Conflicts:
arch/arm/dts/armada-385-amc.dts
arch/arm/dts/armada-xp-theadorable.dts
arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/mtdcore.c | 6 | ||||
-rw-r--r-- | drivers/mtd/nand/spi/gigadevice.c | 79 | ||||
-rw-r--r-- | drivers/mtd/spi/Kconfig | 6 | ||||
-rw-r--r-- | drivers/mtd/spi/sf_probe.c | 1 | ||||
-rw-r--r-- | drivers/mtd/spi/spi-nor-core.c | 14 | ||||
-rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 7 |
6 files changed, 69 insertions, 44 deletions
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index cb7ca38d07..89ac8229f5 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -1051,13 +1051,13 @@ static int mtd_check_oob_ops(struct mtd_info *mtd, loff_t offs, return -EINVAL; if (ops->ooblen) { - u64 maxooblen; + size_t maxooblen; if (ops->ooboffs >= mtd_oobavail(mtd, ops)) return -EINVAL; - maxooblen = ((mtd_div_by_ws(mtd->size, mtd) - - mtd_div_by_ws(offs, mtd)) * + maxooblen = ((size_t)(mtd_div_by_ws(mtd->size, mtd) - + mtd_div_by_ws(offs, mtd)) * mtd_oobavail(mtd, ops)) - ops->ooboffs; if (ops->ooblen > maxooblen) return -EINVAL; diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c index 0bade20808..3681c5eed9 100644 --- a/drivers/mtd/nand/spi/gigadevice.c +++ b/drivers/mtd/nand/spi/gigadevice.c @@ -12,12 +12,11 @@ #endif #include <linux/mtd/spinand.h> -#define SPINAND_MFR_GIGADEVICE 0xc8 +#define SPINAND_MFR_GIGADEVICE 0xC8 +#define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS (1 << 4) +#define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS (3 << 4) -#define GIGADEVICE_STATUS_ECC_MASK GENMASK(5, 4) -#define GIGADEVICE_STATUS_ECC_NO_BITFLIPS (0 << 4) -#define GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS (1 << 4) -#define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4) +#define GD5FXGQ4XEXXG_REG_STATUS2 0xf0 static SPINAND_OP_VARIANTS(read_cache_variants, SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0), @@ -35,8 +34,8 @@ static SPINAND_OP_VARIANTS(update_cache_variants, SPINAND_PROG_LOAD_X4(false, 0, NULL, 0), SPINAND_PROG_LOAD(false, 0, NULL, 0)); -static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) +static int gd5fxgq4xexxg_ooblayout_ecc(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) { if (section) return -ERANGE; @@ -47,38 +46,49 @@ static int gd5f1gq4u_ooblayout_ecc(struct mtd_info *mtd, int section, return 0; } -static int gd5f1gq4u_ooblayout_free(struct mtd_info *mtd, int section, - struct mtd_oob_region *region) +static int gd5fxgq4xexxg_ooblayout_free(struct mtd_info *mtd, int section, + struct mtd_oob_region *region) { if (section) return -ERANGE; - /* Reserve 2 bytes for the BBM. */ - region->offset = 2; - region->length = 62; + /* Reserve 1 bytes for the BBM. */ + region->offset = 1; + region->length = 63; return 0; } -static const struct mtd_ooblayout_ops gd5f1gq4u_ooblayout = { - .ecc = gd5f1gq4u_ooblayout_ecc, - .free = gd5f1gq4u_ooblayout_free, -}; - -static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand, - u8 status) +static int gd5fxgq4xexxg_ecc_get_status(struct spinand_device *spinand, + u8 status) { - if (status) - debug("%s (%d): status=%02x\n", __func__, __LINE__, status); + u8 status2; + struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4XEXXG_REG_STATUS2, + &status2); + int ret; - switch (status & GIGADEVICE_STATUS_ECC_MASK) { + switch (status & STATUS_ECC_MASK) { case STATUS_ECC_NO_BITFLIPS: return 0; - case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS: - return 7; - - case GIGADEVICE_STATUS_ECC_8_BITFLIPS: + case GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS: + /* + * Read status2 register to determine a more fine grained + * bit error status + */ + ret = spi_mem_exec_op(spinand->slave, &op); + if (ret) + return ret; + + /* + * 4 ... 7 bits are flipped (1..4 can't be detected, so + * report the maximum of 4 in this case + */ + /* bits sorted this way (3...0): ECCS1,ECCS0,ECCSE1,ECCSE0 */ + return ((status & STATUS_ECC_MASK) >> 2) | + ((status2 & STATUS_ECC_MASK) >> 4); + + case GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS: return 8; case STATUS_ECC_UNCOR_ERROR: @@ -91,16 +101,21 @@ static int gd5f1gq4u_ecc_get_status(struct spinand_device *spinand, return -EINVAL; } +static const struct mtd_ooblayout_ops gd5fxgq4xexxg_ooblayout = { + .ecc = gd5fxgq4xexxg_ooblayout_ecc, + .free = gd5fxgq4xexxg_ooblayout_free, +}; + static const struct spinand_info gigadevice_spinand_table[] = { - SPINAND_INFO("GD5F1GQ4UC", 0xd1, + SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1), - NAND_ECCREQ(8, 2048), + NAND_ECCREQ(8, 512), SPINAND_INFO_OP_VARIANTS(&read_cache_variants, &write_cache_variants, &update_cache_variants), 0, - SPINAND_ECCINFO(&gd5f1gq4u_ooblayout, - gd5f1gq4u_ecc_get_status)), + SPINAND_ECCINFO(&gd5fxgq4xexxg_ooblayout, + gd5fxgq4xexxg_ecc_get_status)), }; static int gigadevice_spinand_detect(struct spinand_device *spinand) @@ -109,8 +124,8 @@ static int gigadevice_spinand_detect(struct spinand_device *spinand) int ret; /* - * Gigadevice SPI NAND read ID need a dummy byte, - * so the first byte in raw_id is dummy. + * For GD NANDs, There is an address byte needed to shift in before IDs + * are read out, so the first byte in raw_id is dummy. */ if (id[1] != SPINAND_MFR_GIGADEVICE) return 0; diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig index 5671bca24a..d3b007a731 100644 --- a/drivers/mtd/spi/Kconfig +++ b/drivers/mtd/spi/Kconfig @@ -62,6 +62,9 @@ config SF_DEFAULT_MODE The default mode may be provided by the platform to handle the common case when only a single serial flash is present on the system. + Not used for boot with device tree; the SPI driver reads + speed and mode from platdata values computed from + available node. config SF_DEFAULT_SPEED int "SPI Flash default speed in Hz" @@ -71,6 +74,9 @@ config SF_DEFAULT_SPEED The default speed may be provided by the platform to handle the common case when only a single serial flash is present on the system. + Not used for boot with device tree; the SPI driver reads + speed and mode from platdata values computed from + available node. if SPI_FLASH diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c index 7f1378f494..73297e1a0a 100644 --- a/drivers/mtd/spi/sf_probe.c +++ b/drivers/mtd/spi/sf_probe.c @@ -166,7 +166,6 @@ static const struct dm_spi_flash_ops spi_flash_std_ops = { }; static const struct udevice_id spi_flash_std_ids[] = { - { .compatible = "spi-flash" }, { .compatible = "jedec,spi-nor" }, { } }; diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index b7f0733877..c4e2f6a08f 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -524,8 +524,11 @@ static int read_bar(struct spi_nor *nor, const struct flash_info *info) */ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) { - u8 buf[SPI_NOR_MAX_ADDR_WIDTH]; - int i; + struct spi_mem_op op = + SPI_MEM_OP(SPI_MEM_OP_CMD(nor->erase_opcode, 1), + SPI_MEM_OP_ADDR(nor->addr_width, addr, 1), + SPI_MEM_OP_NO_DUMMY, + SPI_MEM_OP_NO_DATA); if (nor->erase) return nor->erase(nor, addr); @@ -534,12 +537,7 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr) * Default implementation, if driver doesn't have a specialized HW * control */ - for (i = nor->addr_width - 1; i >= 0; i--) { - buf[i] = addr & 0xff; - addr >>= 8; - } - - return nor->write_reg(nor, nor->erase_opcode, buf, nor->addr_width); + return spi_mem_exec_op(nor->spi, &op); } /* diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 3215e2431d..ec929760ee 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -106,6 +106,11 @@ const struct flash_info spi_nor_ids[] = { SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) }, + { + INFO("gd25lq128", 0xc86018, 0, 64 * 1024, 256, + SECT_4K | SPI_NOR_DUAL_READ | + SPI_NOR_HAS_LOCK | SPI_NOR_HAS_TB) + }, #endif #ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */ /* ISSI */ @@ -142,6 +147,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("mx25l25655e", 0xc22619, 0, 64 * 1024, 512, 0) }, { INFO("mx66l51235l", 0xc2201a, 0, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66u51235f", 0xc2253a, 0, 64 * 1024, 1024, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("mx66u2g45g", 0xc2253c, 0, 64 * 1024, 4096, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("mx66l1g45g", 0xc2201b, 0, 64 * 1024, 2048, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("mx25l1633e", 0xc22415, 0, 64 * 1024, 32, SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | SECT_4K) }, #endif @@ -187,6 +193,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("s25fl116k", 0x014015, 0, 64 * 1024, 32, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, { INFO("s25fl164k", 0x014017, 0, 64 * 1024, 128, SECT_4K) }, { INFO("s25fl208k", 0x014014, 0, 64 * 1024, 16, SECT_4K | SPI_NOR_DUAL_READ) }, + { INFO("s25fl064l", 0x016017, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("s25fl128l", 0x016018, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, #endif #ifdef CONFIG_SPI_FLASH_SST /* SST */ |