diff options
author | Wolfgang Denk <wd@denx.de> | 2021-09-27 18:42:39 +0300 |
---|---|---|
committer | Tom Rini <trini@konsulko.com> | 2021-09-30 16:08:16 +0300 |
commit | 0cf207ec01cbacae47585fcc26591dd2296507d6 (patch) | |
tree | 573cfefc2ab21a033ae98fa2afbd57f1f6528496 /drivers/mtd | |
parent | 0a50b3c97b3408e52589d873d4c7b54ad365a76c (diff) | |
download | u-boot-0cf207ec01cbacae47585fcc26591dd2296507d6.tar.xz |
WS cleanup: remove SPACE(s) followed by TAB
Signed-off-by: Wolfgang Denk <wd@denx.de>
Diffstat (limited to 'drivers/mtd')
-rw-r--r-- | drivers/mtd/mtdcore.c | 4 | ||||
-rw-r--r-- | drivers/mtd/nand/raw/davinci_nand.c | 2 | ||||
-rw-r--r-- | drivers/mtd/nand/raw/fsl_elbc_nand.c | 2 | ||||
-rw-r--r-- | drivers/mtd/nand/raw/nand_base.c | 10 | ||||
-rw-r--r-- | drivers/mtd/nand/raw/nand_ids.c | 2 | ||||
-rw-r--r-- | drivers/mtd/onenand/onenand_base.c | 4 | ||||
-rw-r--r-- | drivers/mtd/spi/spi-nor-ids.c | 2 | ||||
-rw-r--r-- | drivers/mtd/ubi/crc32.c | 32 |
8 files changed, 29 insertions, 29 deletions
diff --git a/drivers/mtd/mtdcore.c b/drivers/mtd/mtdcore.c index d0351b2c6a..9496903e86 100644 --- a/drivers/mtd/mtdcore.c +++ b/drivers/mtd/mtdcore.c @@ -799,8 +799,8 @@ static bool mtd_device_matches_name(struct mtd_info *mtd, const char *name) * device name * @name: MTD device name to open * - * This function returns MTD device description structure in case of - * success and an error code in case of failure. + * This function returns MTD device description structure in case of + * success and an error code in case of failure. */ struct mtd_info *get_mtd_device_nm(const char *name) { diff --git a/drivers/mtd/nand/raw/davinci_nand.c b/drivers/mtd/nand/raw/davinci_nand.c index ef8e85a002..e4860561f8 100644 --- a/drivers/mtd/nand/raw/davinci_nand.c +++ b/drivers/mtd/nand/raw/davinci_nand.c @@ -39,7 +39,7 @@ #define NAND_TIMEOUT 10240 #define NAND_ECC_BUSY 0xC #define NAND_4BITECC_MASK 0x03FF03FF -#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 +#define EMIF_NANDFSR_ECC_STATE_MASK 0x00000F00 #define ECC_STATE_NO_ERR 0x0 #define ECC_STATE_TOO_MANY_ERRS 0x1 #define ECC_STATE_ERR_CORR_COMP_P 0x2 diff --git a/drivers/mtd/nand/raw/fsl_elbc_nand.c b/drivers/mtd/nand/raw/fsl_elbc_nand.c index 0c1bd7b474..ddfd75d32d 100644 --- a/drivers/mtd/nand/raw/fsl_elbc_nand.c +++ b/drivers/mtd/nand/raw/fsl_elbc_nand.c @@ -716,7 +716,7 @@ static int fsl_elbc_chip_init(int devnum, u8 *addr) nand->bbt_td = &bbt_main_descr; nand->bbt_md = &bbt_mirror_descr; - /* set up nand options */ + /* set up nand options */ nand->options = NAND_NO_SUBPAGE_WRITE; nand->bbt_options = NAND_BBT_USE_FLASH; diff --git a/drivers/mtd/nand/raw/nand_base.c b/drivers/mtd/nand/raw/nand_base.c index 0c26e1d9e6..b533683dfe 100644 --- a/drivers/mtd/nand/raw/nand_base.c +++ b/drivers/mtd/nand/raw/nand_base.c @@ -263,7 +263,7 @@ static void ioread8_rep(void *addr, uint8_t *buf, int len) static void ioread16_rep(void *addr, void *buf, int len) { int i; - u16 *p = (u16 *) buf; + u16 *p = (u16 *) buf; for (i = 0; i < len; i++) p[i] = readw(addr); @@ -905,11 +905,11 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip) if (ret) return ret; - u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; - u32 time_start; + u32 timer = (CONFIG_SYS_HZ * timeo) / 1000; + u32 time_start; - time_start = get_timer(0); - while (get_timer(time_start) < timer) { + time_start = get_timer(0); + while (get_timer(time_start) < timer) { if (chip->dev_ready) { if (chip->dev_ready(mtd)) break; diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c index 3104f879f6..2a50f0b214 100644 --- a/drivers/mtd/nand/raw/nand_ids.c +++ b/drivers/mtd/nand/raw/nand_ids.c @@ -30,7 +30,7 @@ struct nand_flash_dev nand_flash_ids[] = { LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xe8, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 1MiB 3,3V 8-bit", 0xec, 1, SZ_4K, SP_OPTIONS), LEGACY_ID_NAND("NAND 2MiB 3,3V 8-bit", 0xea, 2, SZ_4K, SP_OPTIONS), - LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), + LEGACY_ID_NAND("NAND 4MiB 3,3V 8-bit", 0xd5, 4, SZ_8K, SP_OPTIONS), LEGACY_ID_NAND("NAND 8MiB 3,3V 8-bit", 0xe6, 8, SZ_8K, SP_OPTIONS), #endif diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 09daa0dd36..46aeef258d 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -2306,8 +2306,8 @@ static int flexonenand_get_boundary(struct mtd_info *mtd) /** * flexonenand_get_size - Fill up fields in onenand_chip and mtd_info - * boundary[], diesize[], mtd->size, mtd->erasesize, - * mtd->eraseregions + * boundary[], diesize[], mtd->size, mtd->erasesize, + * mtd->eraseregions * @param mtd - MTD device structure */ static void flexonenand_get_size(struct mtd_info *mtd) diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 4aef1ddd6e..0bff52d5f2 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -76,7 +76,7 @@ const struct flash_info spi_nor_ids[] = { { INFO("at45db321d", 0x1f2700, 0, 64 * 1024, 64, SECT_4K) }, { INFO("at45db641d", 0x1f2800, 0, 64 * 1024, 128, SECT_4K) }, { INFO("at25sl321", 0x1f4216, 0, 64 * 1024, 64, SECT_4K) }, - { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, + { INFO("at26df081a", 0x1f4501, 0, 64 * 1024, 16, SECT_4K) }, #endif #ifdef CONFIG_SPI_FLASH_EON /* EON */ /* EON -- en25xxx */ diff --git a/drivers/mtd/ubi/crc32.c b/drivers/mtd/ubi/crc32.c index 9ce061c861..35820c753e 100644 --- a/drivers/mtd/ubi/crc32.c +++ b/drivers/mtd/ubi/crc32.c @@ -293,8 +293,8 @@ EXPORT_SYMBOL(crc32_be); * * A big-endian CRC written this way would be coded like: * for (i = 0; i < input_bits; i++) { - * multiple = remainder & 0x80000000 ? CRCPOLY : 0; - * remainder = (remainder << 1 | next_input_bit()) ^ multiple; + * multiple = remainder & 0x80000000 ? CRCPOLY : 0; + * remainder = (remainder << 1 | next_input_bit()) ^ multiple; * } * Notice how, to get at bit 32 of the shifted remainder, we look * at bit 31 of the remainder *before* shifting it. @@ -313,14 +313,14 @@ EXPORT_SYMBOL(crc32_be); * This changes the code to: * for (i = 0; i < input_bits; i++) { * remainder ^= next_input_bit() << 31; - * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; - * remainder = (remainder << 1) ^ multiple; + * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; + * remainder = (remainder << 1) ^ multiple; * } * With this optimization, the little-endian code is simpler: * for (i = 0; i < input_bits; i++) { * remainder ^= next_input_bit(); - * multiple = (remainder & 1) ? CRCPOLY : 0; - * remainder = (remainder >> 1) ^ multiple; + * multiple = (remainder & 1) ? CRCPOLY : 0; + * remainder = (remainder >> 1) ^ multiple; * } * * Note that the other details of endianness have been hidden in CRCPOLY @@ -330,19 +330,19 @@ EXPORT_SYMBOL(crc32_be); * order, we can actually do the merging 8 or more bits at a time rather * than one bit at a time: * for (i = 0; i < input_bytes; i++) { - * remainder ^= next_input_byte() << 24; - * for (j = 0; j < 8; j++) { - * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; - * remainder = (remainder << 1) ^ multiple; - * } + * remainder ^= next_input_byte() << 24; + * for (j = 0; j < 8; j++) { + * multiple = (remainder & 0x80000000) ? CRCPOLY : 0; + * remainder = (remainder << 1) ^ multiple; + * } * } * Or in little-endian: * for (i = 0; i < input_bytes; i++) { - * remainder ^= next_input_byte(); - * for (j = 0; j < 8; j++) { - * multiple = (remainder & 1) ? CRCPOLY : 0; - * remainder = (remainder << 1) ^ multiple; - * } + * remainder ^= next_input_byte(); + * for (j = 0; j < 8; j++) { + * multiple = (remainder & 1) ? CRCPOLY : 0; + * remainder = (remainder << 1) ^ multiple; + * } * } * If the input is a multiple of 32 bits, you can even XOR in a 32-bit * word at a time and increase the inner loop count to 32. |