diff options
| author | Weijie Gao <weijie.gao@mediatek.com> | 2023-07-19 12:17:22 +0300 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-08-03 16:40:50 +0300 |
| commit | 585a1a44ee009ee27992a973057ab9b2c676386d (patch) | |
| tree | 7e8871a061d7e75c696dc9fb64c78aa66a01f761 /drivers/net/mtk_eth.h | |
| parent | aef54ea16cacbbdb83ae5615b11964f15d006f75 (diff) | |
| download | u-boot-585a1a44ee009ee27992a973057ab9b2c676386d.tar.xz | |
net: mediatek: add support for GMAC/USB3 PHY mux mode for MT7981
MT7981 has its GMAC2 PHY shared with USB3. To enable GMAC2, mux
register must be set to connect the SGMII phy to GMAC2.
Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
Diffstat (limited to 'drivers/net/mtk_eth.h')
| -rw-r--r-- | drivers/net/mtk_eth.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/drivers/net/mtk_eth.h b/drivers/net/mtk_eth.h index 320266cd82..519986c01e 100644 --- a/drivers/net/mtk_eth.h +++ b/drivers/net/mtk_eth.h @@ -15,27 +15,38 @@ enum mkt_eth_capabilities { MTK_TRGMII_BIT, MTK_TRGMII_MT7621_CLK_BIT, + MTK_U3_COPHY_V2_BIT, + MTK_INFRA_BIT, MTK_NETSYS_V2_BIT, /* PATH BITS */ MTK_ETH_PATH_GMAC1_TRGMII_BIT, + MTK_ETH_PATH_GMAC2_SGMII_BIT, }; #define MTK_TRGMII BIT(MTK_TRGMII_BIT) #define MTK_TRGMII_MT7621_CLK BIT(MTK_TRGMII_MT7621_CLK_BIT) +#define MTK_U3_COPHY_V2 BIT(MTK_U3_COPHY_V2_BIT) +#define MTK_INFRA BIT(MTK_INFRA_BIT) #define MTK_NETSYS_V2 BIT(MTK_NETSYS_V2_BIT) /* Supported path present on SoCs */ #define MTK_ETH_PATH_GMAC1_TRGMII BIT(MTK_ETH_PATH_GMAC1_TRGMII_BIT) +#define MTK_ETH_PATH_GMAC2_SGMII BIT(MTK_ETH_PATH_GMAC2_SGMII_BIT) + #define MTK_GMAC1_TRGMII (MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII) +#define MTK_GMAC2_U3_QPHY (MTK_ETH_PATH_GMAC2_SGMII | MTK_U3_COPHY_V2 | MTK_INFRA) + #define MTK_HAS_CAPS(caps, _x) (((caps) & (_x)) == (_x)) #define MT7621_CAPS (MTK_GMAC1_TRGMII | MTK_TRGMII_MT7621_CLK) #define MT7623_CAPS (MTK_GMAC1_TRGMII) +#define MT7981_CAPS (MTK_GMAC2_U3_QPHY | MTK_NETSYS_V2) + #define MT7986_CAPS (MTK_NETSYS_V2) /* Frame Engine Register Bases */ @@ -56,6 +67,11 @@ enum mkt_eth_capabilities { #define ETHSYS_CLKCFG0_REG 0x2c #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) +/* Top misc registers */ +#define USB_PHY_SWITCH_REG 0x218 +#define QPHY_SEL_MASK 0x3 +#define SGMII_QPHY_SEL 0x2 + /* SYSCFG0_GE_MODE: GE Modes */ #define GE_MODE_RGMII 0 #define GE_MODE_MII 1 |