diff options
| author | Vignesh Raghavendra <vigneshr@ti.com> | 2020-07-06 11:06:53 +0300 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-07-13 18:28:34 +0300 |
| commit | 9eab6fd526c510e8fee4660733a10b756ceddd44 (patch) | |
| tree | b40462aafdc52de0d557247cb9d2f65a4d593f97 /drivers/net | |
| parent | cf9b9942bf3af9e00381f9d51bf60585ef820f97 (diff) | |
| download | u-boot-9eab6fd526c510e8fee4660733a10b756ceddd44.tar.xz | |
net: ti: am65-cpsw-nuss: Set ALE default thread enable
Force default thread to be used for RX as ALE is anyways set to Bypass
mode.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Diffstat (limited to 'drivers/net')
| -rw-r--r-- | drivers/net/ti/am65-cpsw-nuss.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/net/ti/am65-cpsw-nuss.c b/drivers/net/ti/am65-cpsw-nuss.c index e8fe875e70..753a117300 100644 --- a/drivers/net/ti/am65-cpsw-nuss.c +++ b/drivers/net/ti/am65-cpsw-nuss.c @@ -61,6 +61,9 @@ #define AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD 0x3 #define AM65_CPSW_ALE_PN_CTL_REG_MAC_ONLY BIT(11) +#define AM65_CPSW_ALE_THREADMAPDEF_REG 0x134 +#define AM65_CPSW_ALE_DEFTHREAD_EN BIT(15) + #define AM65_CPSW_MACSL_CTL_REG 0x0 #define AM65_CPSW_MACSL_CTL_REG_IFCTL_A BIT(15) #define AM65_CPSW_MACSL_CTL_EXT_EN BIT(18) @@ -364,6 +367,9 @@ static int am65_cpsw_start(struct udevice *dev) writel(AM65_CPSW_ALE_PN_CTL_REG_MODE_FORWARD, common->ale_base + AM65_CPSW_ALE_PN_CTL_REG(0)); + writel(AM65_CPSW_ALE_DEFTHREAD_EN, + common->ale_base + AM65_CPSW_ALE_THREADMAPDEF_REG); + /* PORT x configuration */ /* Port x Max length register */ |