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| author | Pali Rohár <pali@kernel.org> | 2021-12-21 14:20:19 +0300 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2022-01-14 09:47:57 +0300 |
| commit | 94c30f9c8f3cf3032349167be21b837b2d568ea2 (patch) | |
| tree | a38a6f3e10880b010ef95a1775ac357fc1b6b81b /drivers/pci/Kconfig | |
| parent | 35e29e89a38662407d773e01ad6344de6ad268f0 (diff) | |
| download | u-boot-94c30f9c8f3cf3032349167be21b837b2d568ea2.tar.xz | |
arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
Width bits of PCIe Root Port Link Capabilities Register depending of number
of used serdes lanes. As this register is part of PCIe address space and
not serdes address space, move it into pci_mvebu.c driver.
Read number of PCIe lanes from DT property "num-lanes" which is used also
by other PCIe controller drivers in Linux kernel. If this property is
absent then it defaults to 1. This property needs to be set to 4 for every
mvebu board which use PEX_ROOT_COMPLEX_X4 or PEX_BUS_MODE_X4.
Enabling of PCIe port needs to be done afer all registers in PCIe address
space are properly configure. For this purpose use new mvebu-reset driver
(part of system-controller) and remove this code from serdes code.
Because some PCIe ports cannot be enabled individually, it is required to
first setup all PCIe ports and then enable them.
This change contains also all required "num-lanes" and "resets" DTS
properties, to make pci_mvebu.c driver work correctly.
Signed-off-by: Pali Rohár <pali@kernel.org>
Diffstat (limited to 'drivers/pci/Kconfig')
| -rw-r--r-- | drivers/pci/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig index 42f8cb6be0..630d6e6cc5 100644 --- a/drivers/pci/Kconfig +++ b/drivers/pci/Kconfig @@ -265,6 +265,7 @@ config PCI_MVEBU bool "Enable Armada XP/38x PCIe driver" depends on ARCH_MVEBU select MISC + select DM_RESET help Say Y here if you want to enable PCIe controller support on Armada XP/38x SoCs. |