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authorSimon Glass <sjg@chromium.org>2021-08-02 03:54:30 +0300
committerTom Rini <trini@konsulko.com>2021-08-06 02:46:35 +0300
commit0019e5e39f5651af3d8f0af82d445b09248e0f05 (patch)
tree8ea40ef1c4ea4ba89f93c3a99e5de2727d098845 /drivers/pci
parent4afab721f15f96152a5a16342c468cbf6e85272c (diff)
downloadu-boot-0019e5e39f5651af3d8f0af82d445b09248e0f05.tar.xz
pci: msc01: Drop use of DM_PCI
Now that DM_PCI is always enabled we don't need to check it. Drop this old code. Signed-off-by: Simon Glass <sjg@chromium.org>
Diffstat (limited to 'drivers/pci')
-rw-r--r--drivers/pci/pci_msc01.c64
1 files changed, 0 insertions, 64 deletions
diff --git a/drivers/pci/pci_msc01.c b/drivers/pci/pci_msc01.c
index c17da475d0..2f1b688fc3 100644
--- a/drivers/pci/pci_msc01.c
+++ b/drivers/pci/pci_msc01.c
@@ -62,69 +62,6 @@ static int msc01_config_access(struct msc01_pci_controller *msc01,
return 0;
}
-#if !IS_ENABLED(CONFIG_DM_PCI)
-static int msc01_read_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 *value)
-{
- struct msc01_pci_controller *msc01 = hose_to_msc01(hose);
-
- *value = 0xffffffff;
- return msc01_config_access(msc01, PCI_ACCESS_READ, dev, where, value);
-}
-
-static int msc01_write_config_dword(struct pci_controller *hose, pci_dev_t dev,
- int where, u32 value)
-{
- struct msc01_pci_controller *gt = hose_to_msc01(hose);
- u32 data = value;
-
- return msc01_config_access(gt, PCI_ACCESS_WRITE, dev, where, &data);
-}
-
-void msc01_pci_init(void *base, unsigned long sys_bus, unsigned long sys_phys,
- unsigned long sys_size, unsigned long mem_bus,
- unsigned long mem_phys, unsigned long mem_size,
- unsigned long io_bus, unsigned long io_phys,
- unsigned long io_size)
-{
- static struct msc01_pci_controller global_msc01;
- struct msc01_pci_controller *msc01;
- struct pci_controller *hose;
-
- msc01 = &global_msc01;
- msc01->base = base;
-
- hose = &msc01->hose;
-
- hose->first_busno = 0;
- hose->last_busno = 0;
-
- /* System memory space */
- pci_set_region(&hose->regions[0], sys_bus, sys_phys, sys_size,
- PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
-
- /* PCI memory space */
- pci_set_region(&hose->regions[1], mem_bus, mem_phys, mem_size,
- PCI_REGION_MEM);
-
- /* PCI I/O space */
- pci_set_region(&hose->regions[2], io_bus, io_phys, io_size,
- PCI_REGION_IO);
-
- hose->region_count = 3;
-
- pci_set_ops(hose,
- pci_hose_read_config_byte_via_dword,
- pci_hose_read_config_word_via_dword,
- msc01_read_config_dword,
- pci_hose_write_config_byte_via_dword,
- pci_hose_write_config_word_via_dword,
- msc01_write_config_dword);
-
- pci_register_hose(hose);
- hose->last_busno = pci_hose_scan(hose);
-}
-#else
static int msc01_pci_read_config(const struct udevice *dev, pci_dev_t bdf,
uint where, ulong *val, enum pci_size_t size)
{
@@ -192,4 +129,3 @@ U_BOOT_DRIVER(msc01_pci) = {
.probe = msc01_pci_probe,
.priv_auto = sizeof(struct msc01_pci_controller),
};
-#endif