Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- Turris_omnia/mox: SPI NOR and MTD related changes / fixes (Marek)
- a37xx: pci: Misc fixes / optimizations (Pali)
- Espressobin: Fix setting $fdtfile env & changes in MMC detection
  (Pali)
- MMC: mmc_get_op_cond: Allow quiet detection of eMMC (Pali)

1 files changed, 5 insertions, 4 deletions

diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
index 96aa039bdc..1b9bae7cca 100644
--- a/drivers/pci/pci-aardvark.c
+++ b/drivers/pci/pci-aardvark.c
@@ -605,25 +605,26 @@ static void pcie_advk_set_ob_region(struct pcie_advk *pcie, int *wins,
 
 	/*
 	 * The n-th PCIe window is configured by tuple (match, remap, mask)
-	 * and an access to address A uses this window it if A matches the
+	 * and an access to address A uses this window if A matches the
 	 * match with given mask.
 	 * So every PCIe window size must be a power of two and every start
 	 * address must be aligned to window size. Minimal size is 64 KiB
-	 * because lower 16 bits of mask must be zero.
+	 * because lower 16 bits of mask must be zero. Remapped address
+	 * may have set only bits from the mask.
 	 */
 	while (*wins < OB_WIN_COUNT && size > 0) {
 		/* Calculate the largest aligned window size */
 		win_size = (1ULL << (fls64(size) - 1)) |
 			   (phys_start ? (1ULL << __ffs64(phys_start)) : 0);
 		win_size = 1ULL << __ffs64(win_size);
-		if (win_size < 0x10000)
+		win_mask = ~(win_size - 1);
+		if (win_size < 0x10000 || (bus_start & ~win_mask))
 			break;
 
 		dev_dbg(pcie->dev,
 			"Configuring PCIe window %d: [0x%llx-0x%llx] as 0x%x\n",
 			*wins, (u64)phys_start, (u64)phys_start + win_size,
 			actions);
-		win_mask = ~(win_size - 1) & ~0xffff;
 		pcie_advk_set_ob_win(pcie, *wins, phys_start, bus_start,
 				     win_mask, actions);